AD9805JS Analog Devices Inc, AD9805JS Datasheet - Page 11

• Manufacturer Part Number: AD9805JS
• Description: IC CCD SIGNAL PROC 10BIT 64-PQFP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9805JS

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: Microprocessor
• Current - Supply: 86mA
• Mounting Type: Surface Mount
• Package / Case: 64-MQFP, 64-PQFP
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Not Compliant

REGISTER OVERVIEW
MPU Port Map
Table II shows the MPU Port Map. The MPU Port Map is
accessed through pins A0, A1 and A2 of the AD9807/AD9805,
and provides the decoding scheme for the various registers of
the AD9807/AD9805. When writing or reading from any of the
registers, the appropriate bits must be applied to A0–A2.
A2
0
0
0
0
1
1
1
1
Configuration Register/AD9807
The Configuration Register controls three functions: a color
pointer, gain and offset pin configurations, and digital gain
scaling. Figure 5 shows the AD9807 Configuration Register.
Bits 0–2 control the digital scaling function. Setting a bit makes
the corresponding condition true. Resetting Bits 0–2 disables
and bypasses the digital multiplier. Bits 3–5 control the gain
and offset pin distribution. Resetting Bits 3–5 disables and
bypasses the digital subtracter and sets the gain word width to
12. Setting any bit makes the corresponding condition true. For
example, if Bit 3 is set, the 2 LSBs of the gain word become the
2 MSBs of the offset word. If Bit 4 is set, the LSB of the gain
word becomes MSB of the offset word. Bits 6 and 7 direct
register data written to the MPU<7:0> bus to the appropriate
red, green or blue register.
REV. 0
VING
VINB
VINR
CDSCLK1
A1
0
0
1
1
0
0
1
1
GREEN
BLUE
RED
Table II. MPU Port Map Format
CDSCLK2
CDS
CDS
CDS
A0
0
1
0
1
0
1
0
1
PGA
PGA
PGA
STRTLN ADCCLK
Register
Configuration Register
Configuration Register 2
PGA Gain Register
Odd Offset Register
Even Offset Register
Input Offset Register
RESERVED
Bayer Mode
R
G
B
AD9807/AD9805
MUX
CONFIGURATION
CONFIGURATION
REGISTER
REGISTER
3
2
12-BIT/10-BIT
INPUT OFFSET
Figure 4. Block Diagram
REGISTER
REFERENCE
A/D
BANDGAP
VREF
R
G
B
12
–11–
OFFSET<M:0>
R
G
B
SUBTRACTOR
Configuration Register/AD9805
The Configuration Register controls three functions: a color
pointer, gain and offset pin configurations, and digital gain
scaling. Figure 6 shows the AD9805 Configuration Register.
Bits 0–2 control the digital scaling function. Setting a Bit
makes the corresponding condition true. Resetting Bits 0–2
disables and bypasses the digital multiplier. Bits 3–5 control
the gain and offset pin distribution. Resetting Bits 3–5 disables
and bypasses the digital subtracter and sets the gain word width
to 10. Setting any bit makes the corresponding condition true.
If Bit 3 is set, the 2 LSBs of the gain word become the 2 MSBs
of the offset word. If Bit 4 is set, the LSB of the gain word
becomes MSB of the offset word. Bits 6 and 7 direct register
data written to the MPU<7:0> bus to the appropriate red,
green or blue register.
ODD
ODD
ODD
DIGITAL
–
Figure 5. AD9807 Configuration Register Format
Figure 6. AD9805 Configuration Register Format
8-10
R
G
B
EVEN
EVEN
EVEN
7
7
12
6
6
MULTIPLIER
GAIN<N:0>
5
5
DIGITAL
X
4
4
12-10/10-8
3
3
PORT
2
MPU
2
12
1
1
8
I/O
0
0
AD9807/AD9805
12
8X FULL SCALE
4X FULL SCALE
2X FULL SCALE
10-BIT GAIN, 10-BIT OFFSET
11-BIT GAIN, 9-BIT OFFSET
12-BIT GAIN, 8-BIT OFFSET
COLOR0
COLOR1
8X FULL SCALE
4X FULL SCALE
2X FULL SCALE
8-BIT GAIN, 10-BIT OFFSET
9-BIT GAIN, 9-BIT OFFSET
10-BIT GAIN, 8-BIT OFFSET
COLOR0
COLOR1
OEB
DOUT<11:0>/MPU<7:0>
RDB
CSB
WRB
A2
A1
A0