DS1876T+ Maxim Integrated Products, DS1876T+ Datasheet - Page 49

• Manufacturer Part Number: DS1876T+
• Description: IC CTRLR SFP DUAL LDD 28TQFN
• Manufacturer: Maxim Integrated Products
• Type: SFP Laser Controllerr

Specifications of DS1876T+

• Input Type: Logic
• Output Type: Logic
• Interface: I²C
• Current - Supply: 10mA
• Mounting Type: Surface Mount
• Package / Case: 28-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 02h, Register 8Ah: CNFGC
Table 02h, Register 8Bh: DEVICE ADDRESS
8Ah
8Bh
FACTORY DEFAULT
READ ACCESS
WRITE ACCESS
A2h AND B2h MEMORY
MEMORY TYPE
FACTORY DEFAULT
READ ACCESS
WRITE ACCESS
A2h AND B2h MEMORY
MEMORY TYPE
This value becomes the I
is set. If A0h is programmed to this register, the auxiliary memory is disabled. For example, writing xxxx_010x
makes the main device addresses A4h and B4h.
TXDFG2
BITS 1:0
BIT 7
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
______________________________________________________________________________________
BIT 7
SEE
SFP Controller with Dual LDD Interface
TXDFG2: See Figure 9.
0 = FETG2, an internal signal, has no effect on TXDOUT2.
1 = FETG2 is enabled and ORed with other possible signals to create TXDOUT2.
TXDFLT2: See Figure 9.
0 = TXF2 pin has no effect on TXDOUT2.
1 = TXF2 pin is enabled and ORed with other possible signals to create TXDOUT2.
TXDIO2: See Figure 9.
0 = (default) TXD2 input signal is enabled and ORed with other possible signals to create TXDOUT2.
1 = TXD2 input signal has no effect on TXDOUT2.
TXDFG1: See Figure 9.
0 = FETG1, an internal signal, has no effect on TXDOUT1.
1 = FETG1 is enabled and ORed with other possible signals to create TXDOUT1.
TXDFLT1: See Figure 9.
0 = TXF1 pin has no effect on TXDOUT1.
1 = TXF1 pin is enabled and ORed with other possible signals to create TXDOUT1.
TXDIO1: See Figure 9.
0 = (default) TXD1 input signal is enabled and ORed with other possible signals to create TXDOUT1.
1 = TXD1 input signal has no effect on TXDOUT1.
RESERVED
TXDFLT2
SEE
2
C slave address for the main memory when the ASEL bit (Table 02h, Register 88h)
00h
PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
PW2 or (PW1 and RWTBL2)
Common A2h and B2h memory location
Nonvolatile (SEE)
00h
PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
PW2 or (PW1 and RWTBL2)
Common A2h and B2h memory location
Nonvolatile (SEE)
TXDIO2
SEE
TXDFG1
SEE
TXDFLT1
2
3
TXDIO1
2
2
RESERVED
2
1
RESERVED
BIT 0
BIT 0
SEE
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