AD9845BJSTZ Analog Devices Inc, AD9845BJSTZ Datasheet - Page 5

• Manufacturer Part Number: AD9845BJSTZ
• Description: IC CCD SIGNAL PROC 12BIT 48-LQFP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9845BJSTZ

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Supply Voltage Range: 2.7V To 3.6V
• Ic Mounting: SMD
• Tv / Video Case Style: LFCSP
• No. Of Pins: 48
• Msl: MSL 3 - 168 Hours
• Termination Type: SMD
• Sample Rate: 30MSPS
• Data Interface: 3-Wire, Serial
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Digital Ic Case Style: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TIMING SPECIFICATIONS
Parameter
SAMPLE CLOCKS
DATA OUTPUTS
SERIAL INTERFACE
*
Specifications subject to change without notice.
Parameter
AVDD1, AVDD2
DVDD1, DVDD2
DRVDD
Digital Outputs
SHP, SHD, DATACLK
CLPOB, CLPDM, PBLK
SCK, SL, SDATA
VRT, VRB
BYP1-3, CCDIN
Junction Temperature
Lead Temperature (10 sec)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD9845B features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. B
Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
DATACLK, SHP, SHD Clock Period
DATACLK High/Low Pulsewidth
SHP Pulsewidth
SHD Pulsewidth
CLPDM Pulsewidth
CLPOB Pulsewidth
SHP Rising Edge to SHD Falling Edge
SHP Rising Edge to SHD Rising Edge
Internal Clock Delay
Inhibited Clock Period
Output Delay
Output Hold Time
Pipeline Delay
Maximum SCK Frequency
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDATA Valid Hold
SCK Falling Edge to SDATA Valid Read
ABSOLUTE MAXIMUM RATINGS
*
With
Respect
To
AVSS
DVSS
DRVSS
DRVSS
DVSS
DVSS
DVSS
AVSS
AVSS
Min Max
–0.3 +3.9
–0.3 +3.9
–0.3 +3.9
–0.3 DRVDD + 0.3 V
–0.3 DVDD + 0.3
–0.3 DVDD + 0.3
–0.3 DVDD + 0.3
–0.3 AVDD + 0.3
–0.3 AVDD + 0.3
(C
Serial Timing in Figures 21–24.)
L
= 20 pF, f
150
300
SAMP
= 30 MHz, CCD Mode Timing in Figures 5 and 6, AUX Mode Timing in Figure 7,
Unit
V
V
V
V
V
V
V
V
∞C
∞C
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
f
t
t
t
t
t
CP
ADC
SHP
SHD
CDM
COB
S1
S2
ID
INH
OD
H
SCLK
LS
LH
DS
DH
DV
–5–
Model
AD9845BJST –20∞C to +85∞C
THERMAL CHARACTERISTICS
Thermal Resistance
48-Lead LQFP Package
*
q
JA
q
is measured using a 4-layer PCB.
JA
= 56∞C/W*
Min
33
13
5
5
4
2
0
15
10
7.0
10
10
10
10
10
10
Temperature
Range
ORDERING GUIDE
Typ
33
16.7
8.3
8.3
10
20
8.3
16.7
3.0
13
7.6
9
Max
16
Package
Description
LQFP
AD9845B
Package
Option
ST-48
Unit
ns
ns
ns
ns
Pixels
Pixels
ns
ns
ns
ns
ns
ns
Cycles
MHz
ns
ns
ns
ns
ns