AD9845BJSTZ Analog Devices Inc, AD9845BJSTZ Datasheet - Page 14

• Manufacturer Part Number: AD9845BJSTZ
• Description: IC CCD SIGNAL PROC 12BIT 48-LQFP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9845BJSTZ

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Supply Voltage Range: 2.7V To 3.6V
• Ic Mounting: SMD
• Tv / Video Case Style: LFCSP
• No. Of Pins: 48
• Msl: MSL 3 - 168 Hours
• Termination Type: SMD
• Sample Rate: 30MSPS
• Data Interface: 3-Wire, Serial
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Digital Ic Case Style: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9845B
SERIAL INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION
Register
Name
Operation
VGA Gain
Clamp Level
Control
PxGA Gain0
PxGA Gain1
PxGA Gain2
PxGA Gain3
NOTES
1
2
Internal use only. Must be set to 0.
Must be set to 1.
SDATA
SDATA
SCK
SCK
SL
SL
0
1
A0 A1 A2
1
0
0
1
0
1
Address
NOTES
1. RNW = READ-NOT-WRITE. SET HIGH FOR READ OPERATION.
2. TEST BITS = INTERNAL USE ONLY. MUST BE SET LOW.
3. SERIAL DATA FROM THE SELECTED REGISTER IS VALID STARTING AFTER THE FIFTH SCK FALLING EDGE AND IS UPDATED ON
NOTES
1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK.
2. RNW = READ-NOT-WRITE. SET LOW FOR WRITE OPERATION.
3. TEST BITS = INTERNAL USE ONLY. MUST BE SET LOW.
4. SYSTEM UPDATE OF LOADED REGISTERS OCCURS ON SL RISING EDGE.
t
t
DS
DS
SCK FALLING EDGES.
0
0
1
1
0
0
1
1
RNW
RNW
0
0
0
0
1
1
1
1
0
1
t
t
LS
LS
A0
A0
Channel Select Power-Down
CCD/AUX1/2 Modes
LSB
Color Steering Mode
Selection
LSB
LSB
LSB
LSB
D0
LSB
t
t
DH
DH
A1
A1
D1
A2
0
TEST BIT
TEST BIT
Figure 22. Serial Readback Operation
D2
0
0
Figure 21. Serial Write Operation
Table I. Internal Register Map
D0
D0
t
D3
PxGA
On/Off
DV
D1
D1
–14–
D4
Software OB Clamp
Reset
Clock Polarity Select for
SHP/SHD/CLP/DATA
D2
D2
D3
D3
D5
On/Off
MSB
MSB
MSB
MSB
D4
Data Bits
D4
D5
D5
D6
D6
D6
0
X
X
X
X
D7
1
D7
D8
D8
D7
1
MSB
0
X
X
X
X
2
1
D9
D9
t
t
LH
LH
D8
0
X
0
X
X
X
X
D10
D10
1
1
D9
0
MSB
X
Three-
State
X
X
X
X
1
REV. B
D10
0
X
X
X
X
X
X
X
1