AD9948KCPZRL Analog Devices Inc, AD9948KCPZRL Datasheet - Page 26

• Manufacturer Part Number: AD9948KCPZRL
• Description: IC CCD SIGNAL PROCESSOR 40-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 10-Bitr

Specifications of AD9948KCPZRL

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 40-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

AD9948
HORIZONTAL TIMING SEQUENCE EXAMPLE
Figure 24 shows an example CCD layout. The horizontal regis-
ter contains 28 dummy pixels, which will occur on each line
clocked from the CCD. In the vertical direction, there are 10
optical black (OB) lines at the front of the readout and two at
the back of the readout. The horizontal direction has four OB
pixels in the front and 48 in the back.
To configure the AD9948 horizontal signals for this CCD, three
sequences can be used. Figure 25 shows the first sequence, to be
used during vertical blanking. During this time, there are no
CLPOB
CCDIN
H1/H3
H2/H4
HBLK
PBLK
SHP
SHD
SEQUENCE 1: VERTICAL BLANKING
INVALID PIX
28 DUMMY PIXELS
VERTICAL SHIFT
4 OB PIXELS
V
Figure 25. Horizontal Sequence during Vertical Blanking
EFFECTIVE IMAGE AREA
HORIZONTAL CCD REGISTER
Figure 24. Example CCD Configuration
DUMMY
H
48 OB PIXELS
–26–
valid OB pixels from the sensor, so the CLPOB signal is not
used. PBLK may be enabled during this time, because no valid
data is available.
Figure 26 shows the recommended sequence for the vertical OB
interval. The clamp signals are used across the whole lines in
order to stabilize the clamp loop of the AD9948.
Figure 27 shows the recommended sequence for the effective
pixel readout. The 48 OB pixels at the end of each line are used
for the CLPOB signal.
10 VERTICAL OB LINES
2 VERTICAL OB LINES
INVALID PIXELS
USE SEQUENCE 3
USE SEQUENCE 2
SEQUENCE 2 (OPTIONAL)
REV. 0
VERT SHIFT