SI3019-F-FM Silicon Laboratories Inc, SI3019-F-FM Datasheet - Page 60

• Manufacturer Part Number: SI3019-F-FM
• Description: IC VOICE DAA GCI/PCM/SPI 20-QFN
• Manufacturer: Silicon Laboratories Inc
• Series: -r

Specifications of SI3019-F-FM

• Function: Data Access Arrangement (DAA)
• Interface: GCI, PCM, SPI
• Number Of Circuits: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 8.5mA
• Power (watts): *
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-VFQFN Exposed Pad
• Includes: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Si3050 + Si3011/18/19
CIR1: OH
Data that is received must be consistent and match for at least two consecutive frames to be considered valid.
When a new command or status is communicated via the C/I bits, the data must be sent for at least two
consecutive frames to be recognized by the Si3050. The following steps describe the protocol of how C/I bits are
stored, detected, and validated. This is illustrated in Figure 49.
1. The current state of the C/I bits are stored in a primary register P. If the received C/I bits are identical to this
2. Upon receipt of an SC channel with C/I bits that differ from the current state, these new C/I bits are immediately
3. The C/I bits in the SC channel received in the frame immediately after the SC channel just stored in S are
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current state, no action is taken.
latched into a secondary register S.
compared with the C/I bits in the S register.
a. If the C/I bits in these two channels are identical, then the C/I bits in the S register are loaded into the P
b. If a set of C/I bits is latched into the S register and the subsequent set of C/I bits received does not match
c. If the C/I bits in the SC channel received immediately after the SC channel just stored in S do not match the
register and are considered a valid change of C/I bits. The Si3050 then responds accordingly to the changed
C/I bits.
either the S or P registers, then the newly received set of C/I bits are latched into the S register. This
continues to occur as long as the subsequent set of C/I bits received differs from the C/I bits in the S and
P registers.
C/I bits stored in S, but DO match the C/I bits stored in P, then the single set of C/I bits stored in the S latch
are invalidated, and the current state of the C/I bits in P remains unchanged.
Receive New
Receive New
Figure 49. Protocol for Receiving C/I Bits in the Si3050
CI Code
Store in S
C/I Code
= P?
= S?
= P?
No
No
No
Yes
Yes
Yes
Rev. 1.4
With New C/I Bits
Load C/I Register
P: C/I Primary Register Contents
S: C/I Secondary Register Contents