STMPE24M31QTR STMicroelectronics, STMPE24M31QTR Datasheet - Page 11

• Manufacturer Part Number: STMPE24M31QTR
• Description: IC SENSOR S-TOUCH 24CH 40QFN
• Manufacturer: STMicroelectronics
• Series: S-Touch™r
• Type: Capacitiver

Specifications of STMPE24M31QTR

• Number Of Inputs/keys: 24 Key
• Data Interface: I²C
• Data Rate/sampling Rate (sps, Bps): 100k, 400k
• Voltage Reference: External
• Voltage - Supply: 1.65 V ~ 1.95 V
• Current - Supply: 900µA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-VQFN
• Output Type: Logic
• Interface: I²C
• Input Type: Logic
• Supply Voltage: 1.8 V
• Number Of Channels: 24
• Dimensions: 5 mm L x 5 mm W x 0.85 mm H
• Temperature Range: - 40 C to + 85 C
• Termination Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-10380-2

STMPE16M31, STMPE24M31
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter
releases the SDA after sending eight bits of data. During the ninth bit, the receiver pulls the
SDA low to acknowledge the receipt of the eight bits of data. The receiver may leave the
SDA in high state if it would to not acknowledge the receipt of the data.
Data input
The device samples the data input on SDA on the rising edge of the SCL. The SDA signal
must be stable during the rising edge of SCL and the SDA signal must change only when
SCL is driven low.
Memory addressing
For the bus master to communicate to the slave device, the bus master must initiate a Start
condition and be followed by the slave device address. Accompanying the slave device
address, there is a Read/W bit (R/W). The bit is set to 1 for Read and 0 for Write operation.
If a match occurs on the slave device address, the corresponding device gives an
acknowledgement on the SDA during the 9
from the bus by not responding to the transaction. The register memory map of the device is
8-bit address width. Therefore, the maximum number of register is 256 registers of 8-bit
width.
Table 6
Table 6.
Mode
Read
Write
illustrates the device operating modes that are supported.
Device operation modes
Bytes
≥1
≥1
START, Device Address, R/W
=0, Base register Address to be read
ReSTART, Device Address, R/W
=1, Data Read, STOP
If no STOP is issued, the Data Read can be continuously
preformed. The address is automatically incremented on
subsequent data read.
START, Device Address, R/W
=0, Register Address to be written, Data Write, STOP
If no STOP is issued, the Data Write can be continuously
performed. The address is automatically incremented on
subsequent write.
Doc ID 16174 Rev 2
th
bit time. If there is no match, it deselects itself
Initial sequence
I
2
C interface module
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