AD698APZ Analog Devices Inc, AD698APZ Datasheet - Page 7

• Manufacturer Part Number: AD698APZ
• Description: IC LVDT SIGNAL COND 28-PLCC
• Manufacturer: Analog Devices Inc
• Type: Signal Conditionerr

Specifications of AD698APZ

• Input Type: Voltage
• Output Type: Voltage
• Interface: LVDT
• Current - Supply: 15mA
• Mounting Type: Surface Mount
• Package / Case: 28-LCC (J-Lead)
• Bandwidth: 20kHz
• Supply Voltage Min: 13V
• Supply Voltage Max: 36V
• Digital Ic Case Style: LCC
• No. Of Pins: 28
• Operating Temperature Range: -40°C To +85°C
• Msl: MSL 5 - 48 Hours
• Supply Voltage Range: 13V To 36V
• Audio Ic Case Style: PLCC
• Base Number: 698
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REV. B
6. Referring to Figure 9, for V
7. C2, C3 and C4 are a function of the desired bandwidth of
D. Set the Full-Scale Output Voltage
8. To compute R2, which sets the AD698 gain or full-scale
Multiply the primary excitation voltage by the VTR to get
the expected secondary voltage at mechanical full scale. For
example, for an LVDT with a sensitivity of 2.4 mV/V/mil and
a full scale of 0.1 inch, the VTR = 0.0024 V/V/Mil 100
mil = 0.24. Assuming the maximum excitation of 3.5 V rms,
the maximum secondary voltage will be 3.5 V rms 0.24 =
0.84 V rms, which is in the acceptable range.
Conversely the VTR may be measured explicitly. With the
LVDT energized at its typical drive level V
by the manufacturer, set the core displacement to its me-
chanical full-scale position and measure the output V
the secondary. Compute the LVDT voltage transformation
ratio, VTR. VTR = V
for V
For situations where LVDT sensitivity is low, or the me-
chanical FS is a small fraction of the total stroke length, an
input excitation of more than 3.5 V rms may be needed. In
this case a voltage divider network may be placed across the
LVDT primary to provide smaller voltage for the +BIN and
–BIN input. If, for example, a network was added to divide
the B Channel input by 1/2, then the VTR should also be re-
duced by 1/2 for the purpose of component selection.
Check the power supply voltages by verifying that the peak
values of V
ages at +V
amplitude determining component R1 as shown by the curve
in Figure 9.
the AD698 position measurement subsystem. They should
be nominally equal values.
If the desired system bandwidth is 250 Hz, then
See Figures 14, 15 and 16 for more information about
AD698 bandwidth and phase characterization.
output range, several pieces of information are needed:
a. LVDT sensitivity, S
PRI
30
25
20
15
10
5
0
0.01
C2 = C3 = C4 = 10
C2 = C3 = C4 = 10
Figure 9. Excitation Voltage V
= 3 V. VTR = 0.24.
S
A
and –V
and V
0.1
B
S
.
are at least 2.5 volts less than the volt-
SEC
//VPRI. For the E100, V
-4
1
–4
S
V rms
Farad Hz/250 Hz = 0.4 F
R1 – k
Farad Hz/f
= 15 V, select the value of the
10
5UBSYSTEM
EXC
PRI
100
vs. R1
, as indicated
SEC
(Hz)
= 0.72 V
SEC
1k
of
–7–
E. Optional Offset of Output Voltage Swing
9. Selections of R3 and R4 permit a positive or negative output
Figure 11. V
( 0.1 Inch)
This will produce a response shown in Figure 11.
In Equation (2) set V
positive offset is desired, let R4 be open circuit. Rearranging
Equation (2) and solving for R3
b. Full-scale core displacement from null, d
S
scale. The VTR should be converted to units of V/V.
For a full-scale displacement of d inches, voltage out of the
AD698 is computed as
V
Pin 21, shown in Figure 7.
Solving for R2,
For V
inch full-scale displacement (0.2 inch span)
V
shown in Figure 10.
Figure 10. V
ment ( 0.1 Inch)
voltage offset adjustment.
For no offset adjustment R3 and R4 should be open circuit.
To design a circuit producing a 0 V to +10 V output for a
displacement of +0.1 inch, set V
and solve Equation (1) for R2.
OUT
OUT
d = VTR and also equals the ratio A/B at mechanical full
V
OUT
OS
is measured with respect to the signal reference,
as a function of displacement for the above example is
R2
= 10 V full-scale range (20 V span) and d = 0.1
OUT
1.2 V
R3
OUT
( 5 V Full Scale) vs. Core Displacement
V
R2
2.4
–0.1
–0.1
OUT
1.2 R2
( 10 V Full Scale) vs. Core Displace-
OS
R2
V
V
= S
V
OS
OUT
= 5 V and solve for R3 and R4. Since a
+10
S d 500 A
OUT
0.2 500 A
+5
–5
20V
(VOLTS)
(VOLTS)
–10
R3 2 k
V
d
– 2 k
OUT
500 A
1
+0.1d (INCHES)
+0.1d (INCHES)
OUT
7.02 k
to +10 V, d = 0.2 inch
–
83. 3 k
R 4
R2
1
2 k
AD698
(2)
(1)