SI3016-F-FS Silicon Laboratories Inc, SI3016-F-FS Datasheet - Page 21

• Manufacturer Part Number: SI3016-F-FS
• Description: IC ISOMODEM LINE-SIDE DAA 16SOIC
• Manufacturer: Silicon Laboratories Inc
• Type: Chipsetr

Specifications of SI3016-F-FS

• Package / Case: 16-SOIC (3.9mm Width)
• Data Format: V.90
• Baud Rates: 56k
• Interface: Serial
• Voltage - Supply: 3.3V, 5V
• Mounting Type: Surface Mount
• Product: Modem Chip
• Supply Current: 0.3 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In systems where the caller ID data is passed on the
phone line between the first and second rings, the
following method should be utilized to capture the caller
ID data:
1. After identifying a ring signal using one of the
2. Set the OFF/SQL2 bit.This bit resets the ac coupling
3. Assert the MODE bit and then the ONHM bit. This
4. The low-power ADC (which is powered from the
5. Clear the ONHM, MODE, and OFF/SQL2 bits after
In systems where the caller ID data is preceded by a
line polarity (battery) reversal, the following method
should be used to capture the caller ID data:
1. Enable full wave rectified ring detection with the
2. Monitor the RDTP and RDTN register bits to identify
3. Once the signal has been identified as a battery
4. Assert the MODE bit and then the ONHM bit. This
5. The low-power ADC (which is powered from the
methods described in "4.11. Ring Detection" on page
18, determine when the first ring has completed.
network on the ring input in preparation for the caller
ID data. This bit should not be cleared until after the
caller ID data has been received.
enables the lower current caller ID ADC.
system chip, allowing for approximately 7 µA current
draw from the line) then digitizes the caller ID data
passed across the RNG 1/2 pins and presents the
data to the DSP via the SDO signal internal to the
integrated system-side module.
the caller ID data has been received but prior to the
start of the second ring.
RFWE bit.
whether a polarity reversal or a ring signal has
occurred. A polarity reversal will trip either the RDTP
or RDTN ring detection bits, and thus the full-wave
ring detector must be used to distinguish a polarity
reversal from a ring. The lowest specified ring
frequency is 15 Hz; therefore, if a battery reversal
occurs, the DSP should wait a minimum of 40 ms to
verify that the event observed is a battery reversal
and not a ring signal. This time is greater than half
the period of the longest ring signal. If another edge
is detected during this 40 ms pause, this event is
characterized as a ring signal and not a battery
reversal.
reversal, the ac coupling network on the ring input
must be reset in preparation for the caller ID data.
Set the OFF/SLQ2 bit. This bit should not be cleared
until after the caller ID data has been received.
enables the lower current caller ID ADC.
system chip, allowing for approximately 7 µA current
draw from the line) then digitizes the caller ID data
Rev. 1.0
6. Clear the ONHM, MODE, and OFF/SLQ2 bits after
4.18.2. Type II Caller ID
Type II Caller ID sends the CID data while the DAA is
off-hook. This mode is often referred to as caller ID/
call waiting (CID/CW). To receive the CID data while off-
hook, the following procedure should be used (also see
Figure 15):
1. The Caller Alert Signal (CAS) tone is sent from the
2. The DAA must then check to see if there is another
3. Immediately after returning to an off-hook state, the
passed across the RNG 1/2 pins and presents the
data to the DSP via the SDO signal internal to the
system-side module.
the caller ID data has been received but prior to the
start of the second ring.
Central Office (CO) and is digitized along with the
line data. The host processor must detect the
presence of this tone.
parallel device on the same line. This is
accomplished by briefly going on-hook, measuring
the line voltage, and then returning to an off-hook
state.
ONHM bit must be set and left enabled for at least
30 ms. This allows the line voltage to settle before
transmitting or receiving any data. After 30 ms, the
ONHM bit should be disabled to allow normal data
transmission and reception.
a. Set the CALD bit to 1. This disables the
b. With the OH bit set to 1 and the ONHM bit set to
c. Read the LVCS bits to determine the state of the
d. If the LVCS bits read the typical on-hook line
e. If the LVCS bits read well below the typical on-
f. Set the MODE bit to 0 to return to an off-hook
calibration that automatically occurs when going
off-hook.
0, set the MODE bit to 1. This forces the DAA to
go on-hook and disables the off-hook counter
that is normally enabled when going back off-
hook.
line.
voltage, there are no parallel devices active on
the line, and CID data reception can be
continued.
hook line voltage, then there are one or more
devices present and active on the same line that
are not compliant with Type II CID. CID data
reception should not be continued.
state.
Si3016
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