SI3010-F-GS Silicon Laboratories Inc, SI3010-F-GS Datasheet - Page 23

• Manufacturer Part Number: SI3010-F-GS
• Description: IC ISOMODEM LINE-SIDE 16SOIC
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3010-F-GS

• Data Format: V.92
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Baud Rates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

4.9. Fast Connect
In modem applications that require fast connection
times, it is possible to reduce the length of the
handshake.
Additional modem handshaking control can be adjusted
through the registers shown in Table 11. These registers
are most useful if the user has control of both the
originating and answering modems.
When the fast connect settings are used, there may be
unintended data received initially. The host must
tolerate these bytes.
Register
S1E
S1F
S20
S21
S22
S23
S24
S34
S35
VDDH
Name
TSOD
RSOL
TSOL
VDDL
ATTD
TASL
TATL
UNL
Transmit Answer Tone Length
Answer Tone to Transmit Delay
Unscrambled Ones Length—V.22
Transmit Scrambled Ones Delay—V.22
Transmit Scrambled Ones Length—V.22
V.22/22b Data Delay Low
V.22/22b Data Delay High
Answer Tone Length
(only used in S1E [TATL] = 0x00)
Receive V.22 Scrambled Ones Length
Table 11. V.22/Bell212 Handshaking Control Registers
Function
Rev. 1.0
4.10. Clock Generation Subsystem
The Si2401 contains an on-chip clock generator. Using
a single master clock input, the Si2401 can generate all
modem sample rates necessary to support V.22bis,
V.22/Bell212A, and V.21/Bell103 standards and a
9.6 kHz rate for audio playback. Either a 27 MHz or
4.9152 MHz clock on XTALI or a 4.9152 MHz crystal
across XTALI and XTALO form the master clock for the
Si2401. This clock source is sent to an internal phase-
locked loop (PLL) that generates all necessary internal
system clocks. The PLL has a settling time of ~1 ms.
Data on RXD should not be sent to the device prior to
settling of the PLL. By default, the Si2401 assumes a
4.9152 MHz clock input. If a 27 MHz clock on XTALI is
used, a pulldown resistor <10 k Ω must be placed
between GPIO4 (Si2401, pin 11) and GND.
(256) 5/3 ms
53.3 ms
5/3 ms
5/3 ms
5/3 ms
5/3 ms
5/3 ms
5/3 ms
Units
1 s
Default
0xCB
0x2D
0x5D
0xA2
0x5A
0xA2
0x03
0x09
0x08
Si2401
Connect
Fast
00
00
00
00
00
00
00
F0
00
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