PCA9555PW/DG,118 NXP Semiconductors, PCA9555PW/DG,118 Datasheet - Page 11

• Manufacturer Part Number: PCA9555PW/DG,118
• Description: IC I/O EXPANDER I2C 16B 24TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9555PW/DG,118

• Package / Case: 24-TSSOP
• Interface: I²C, SMBus
• Number Of I /o: 16
• Interrupt Output: Yes
• Frequency - Clock: 400kHz
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Includes: POR
• Logic Family: SDA, SCL
• Operating Supply Voltage: 2.3 V to 5.5 V
• Power Dissipation: 200 mW
• Operating Temperature Range: - 40 C to + 85 C
• Logic Type: I2C Bus
• Mounting Style: SMD/SMT
• Output Current: +/- 50 mA
• Output Voltage: 4 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935286939118; PCA9555PW/DG-T; PCA9555PW/DG-T

NXP Semiconductors
PCA9555_8
Product data sheet
Fig 12. Read from register
SDA
(cont.)
Remark: Transfer can be stopped at any time by a STOP condition.
S
START condition
S
(repeated)
START condition
6.5.2 Reading the port registers
0
0
1
slave address
1
0
slave address
0
In order to read data from the PCA9555, the bus master must first send the PCA9555
address with the least significant bit set to a logic 0 (see
address”). The command byte is sent after the address and determines which register will
be accessed. After a restart, the device address is sent again, but this time the least
significant bit is set to a logic 1. Data from the register defined by the command byte will
then be sent by the PCA9555 (see
into the register on the falling edge of the acknowledge clock pulse. After the first byte is
read, additional bytes may be read but the data will now reflect the information in the other
register in the pair. For example, if you read Input Port 1, then the next byte read would be
Input Port 0. There is no limitation on the number of data bytes received in one read
transmission but the final byte received, the bus master must not acknowledge the data.
0 A2 A1 A0
0 A2 A1 A0 1
acknowledge
from slave
acknowledge
R/W
from slave
0
R/W
A
A
MSB
Rev. 08 — 22 October 2009
COMMAND BYTE
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
upper byte of register
data from lower or
DATA (first byte)
acknowledge
from slave
Figure
16-bit I
LSB
A
12,
A
acknowledge
from master
(cont.)
2
Figure 13
C-bus and SMBus I/O port with interrupt
MSB
lower byte of register
data from upper or
DATA (last byte)
and
Figure 8 “PCA9555 device
Figure
no acknowledge
from master
14). Data is clocked
LSB
PCA9555
© NXP B.V. 2009. All rights reserved.
NA
002aac222
P
STOP
condition
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