PCA9554TS,118 NXP Semiconductors, PCA9554TS,118 Datasheet - Page 8

• Manufacturer Part Number: PCA9554TS,118
• Description: IC I/O EXPANDER I2C 8B 20SSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9554TS,118

• Package / Case: 20-SSOP
• Interface: I²C, SMBus
• Number Of I /o: 8
• Interrupt Output: Yes
• Frequency - Clock: 400kHz
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Includes: POR
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-2026-2; 935276771118; PCA9554TS-T

NXP Semiconductors
PCA9554_9554A_7
Product data sheet
6.1.4 Register 2 - Polarity Inversion register
6.1.5 Register 3 - Configuration register
6.2 Power-on reset
This register allows the user to invert the polarity of the Input Port register data. If a bit in
this register is set (written with ‘1’), the corresponding Input Port data is inverted. If a bit in
this register is cleared (written with a ‘0’), the Input Port data polarity is retained.
Table 6.
Legend: * default value.
This register configures the directions of the I/O pins. If a bit in this register is set, the
corresponding port pin is enabled as an input with high-impedance output driver. If a bit in
this register is cleared, the corresponding port pin is enabled as an output. At reset, the
I/Os are configured as inputs with a weak pull-up to V
Table 7.
Legend: * default value.
When power is applied to V
PCA9554/PCA9554A in a reset condition until V
reset condition is released and the PCA9554/PCA9554A registers and state machine will
initialize to their default states. Thereafter, V
device.
For a power reset cycle, V
operating voltage.
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
Symbol
N7
N6
N5
N4
N3
N2
N1
N0
Symbol
C7
C6
C5
C4
C3
C2
C1
C0
Register 2 - Polarity Inversion register bit description
Register 3 - Configuration register bit description
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 07 — 13 November 2006
DD
DD
must be lowered below 0.2 V and then restored to the
, an internal Power-On Reset (POR) holds the
Value
0*
0*
0*
0*
0*
0*
0*
0*
Value
1*
1*
1*
1*
1*
1*
1*
1*
8-bit I
Description
inverts polarity of Input Port register data
Description
configures the directions of the I/O pins
0 = Input Port register data retained (default value)
1 = Input Port register data inverted
0 = corresponding port pin enabled as an output
1 = corresponding port pin configured as input
(default value)
DD
2
PCA9554/PCA9554A
C-bus and SMBus I/O port with interrupt
must be lowered below 0.2 V to reset the
DD
has reached V
DD
.
POR
. At that point, the
© NXP B.V. 2006. All rights reserved.
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