MAX7322AEE+ Maxim Integrated Products, MAX7322AEE+ Datasheet - Page 8

• Manufacturer Part Number: MAX7322AEE+
• Description: IC I/O EXPANDER I2C 4B 16QSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX7322AEE+

• Interface: I²C
• Number Of I /o: 4
• Interrupt Output: Yes
• Frequency - Clock: 400kHz
• Voltage - Supply: 1.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-QSOP
• Includes: POR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I
4 Push-Pull Outputs and 4 Inputs
On initial power-up, the MAX7322 cannot decode the
address inputs AD2 and AD0 fully until the first I
transmission. AD0 and AD2 initially appear to be con-
nected to V+ or GND. This is important because the
address selection determines the power-up logic state,
and whether pullups are enabled. However, at power-
up, the I
impedance at the pins of every device (master or slave)
connected to the bus, including the MAX7322. This is
guaranteed as part of the I
address inputs AD2 and AD0 that are connected to
SDA or SCL normally appear at power-up to be connect-
ed to V+. The port selection logic uses AD0 to select
whether pullups are enabled for ports I2 and I3, and to
set the initial logic state for ports O0 and O1. AD2
selects whether pullups are enabled for ports I4 and I5
and sets the internal logic state for ports O6 and O7. The
rule is that a logic-high, SDA, or SCL connection selects
the pullups and sets the default logic state high. A logic-
low deselects the pullups and sets the default logic state
low (Table 2). This means that the port configuration is
correct on power-up for a standard I
where SDA or SCL are pulled up to V+ by the external I
pullup resistors.
There are circumstances where the assumption that
SDA = SCL = V+ on power-up is not true—for example,
Table 2. MAX7322 Address Map
8
CONNECTION
GND
GND
GND
GND
AD2
SDA
SDA
SDA
SDA
SCL
SCL
SCL
SCL
2
V+
V+
V+
V+
_______________________________________________________________________________________
C Port Expander with
PIN
2
GND
GND
GND
GND
AD0
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
C SDA and SCL bus interface lines are high
V+
V+
V+
V+
A6
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DEVICE ADDRESS
A4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
C specification. Therefore,
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
2
C configuration,
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
O7
OUTPUTS POWER—UP DEFAULT
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
2
2
C
C
O6 I5 I4 I3
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
in applications in which there is legitimate bus activity
during power-up. Also, if SDA and SCL are terminated
with pullup resistors to a different supply voltage than
the MAX7322’s supply voltage, and if that pullup supply
rises later than the MAX7322’s supply, then SDA or
SCL may appear at power-up to be connected to GND.
In such applications, use the four address combina-
tions that are selected by connecting address inputs
AD2 and AD0 to V+ or GND (shown in bold in Table 2).
These selections are guaranteed to be correct at
power-up, independent of SDA and SCL behavior. If
one of the other 12 address combinations is used, an
unexpected combination of pullups might be asserted
until the first I
sarily the MAX7322) is put on the bus, and an unexpect-
ed combination of ports may initialize as logic-low
outputs instead of inputs or logic-high outputs.
Port inputs switch at CMOS logic levels as determined by
the expander’s supply voltage, and are overvoltage toler-
ant to +6V, independent of the expander’s supply voltage.
All four input ports are monitored for changes since the
expander was last accessed through the serial inter-
face. The state of the I/O ports is stored in an internal
Inputs
I2
2
C transmission (to any device, not neces-
O1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
Port Input Transition Detection
O0
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
O7 O6
40kΩ INPUT PULLUPS
— — — —
— — Y
— — Y
— — Y
I5
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
ENABLED
I4 I3 I2 O1 O0
Y
Y
Y
Y
Y
Y
Y
Y
Y — —
Y
Y
Y
— —
— —
Y
Y
Y
Y
Y
Y
Y
Y
Y
Port Inputs
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y