MAX7322AEE+ Maxim Integrated Products, MAX7322AEE+ Datasheet - Page 10

• Manufacturer Part Number: MAX7322AEE+
• Description: IC I/O EXPANDER I2C 4B 16QSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX7322AEE+

• Interface: I²C
• Number Of I /o: 4
• Interrupt Output: Yes
• Frequency - Clock: 400kHz
• Voltage - Supply: 1.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-QSOP
• Includes: POR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I
4 Push-Pull Outputs and 4 Inputs
SDA operates as both an input and an open-drain out-
put. A pullup resistor, typically 4.7kΩ, is required on
SDA. SCL operates only as an input. A pullup resistor,
typically 4.7kΩ, is required on SCL if there are multiple
masters on the 2-wire interface, or if the master in a sin-
gle-master system has an open-drain SCL output.
Each transmission consists of a START condition sent
by a master, followed by the MAX7322’s 7-bit slave
address plus R/W bit, one or more data bytes, and
finally a STOP condition
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, the master
issues a STOP (P) condition by transitioning SDA from
low to high while SCL is high. The bus is then free for
another transmission (Figure 2).
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 3).
Figure 2. START and STOP Conditions
10
SDA
SCL
2
CONDITION
C Port Expander with
______________________________________________________________________________________
START
S
(Figure 2).
START and STOP Conditions
Bit Transfer
CONDITION
STOP
P
The acknowledge bit is a clocked 9th bit the recipient
uses to acknowledge receipt of each byte of data
(Figure 4). Each byte transferred effectively requires 9
bits. The master generates the 9th clock pulse, and the
recipient pulls down SDA during the acknowledge
clock pulse, such that the SDA line is stable low during
the high period of the clock pulse. When the master is
transmitting to the MAX7322, the MAX7322 generates
the acknowledge bit because the device is the recipi-
ent. When the MAX7322 is transmitting to the master,
the master generates the acknowledge bit because the
master is the recipient.
Figure 3. Bit Transfer
Figure 4. Acknowledge
TRANSMITTER
SDA
SCL
RECEIVER
SDA BY
SDA BY
SCL
CONDITION
START
DATA LINE STABLE;
S
DATA VALID
1
CHANGE OF DATA
ALLOWED
2
FOR ACKNOWLEDGMENT
CLOCK PULSE
8
Acknowledge
9