PCA9674N,112 NXP Semiconductors, PCA9674N,112 Datasheet - Page 14
![IC I/O EXPANDER I2C 8B 16DIP](/photos/6/52/65287/568-16-dip_sot38-4_sml.jpg)
PCA9674N,112
Manufacturer Part Number
PCA9674N,112
Description
IC I/O EXPANDER I2C 8B 16DIP
Manufacturer
NXP Semiconductors
Datasheet
1.PCA9674ABS118.pdf
(32 pages)
Specifications of PCA9674N,112
Interface
I²C
Number Of I /o
8
Interrupt Output
Yes
Frequency - Clock
1MHz
Voltage - Supply
2.3 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Through Hole
Package / Case
16-DIP (0.300", 7.62mm)
Includes
POR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-4076-5
935283188112
PCA9674N
PCA9674N
935283188112
PCA9674N
PCA9674N
NXP Semiconductors
PCA9674_PCA9674A_5
Product data sheet
Fig 13. Write mode (output)
Fig 14. Read input port register
read from
data into
SDA
port
port
SCL
INT
A LOW-to-HIGH transition of SDA while SCL is HIGH is defined as the STOP condition (P). Transfer of data can be stopped at
any moment by a STOP condition. When this occurs, data present at the last acknowledge phase is valid (Output mode). Input
data is lost.
data output from port
P5 output voltage
P5 pull-up output current
INT
write to port
S A6
START condition
SDA
1
A5 A4 A3 A2 A1 A0 0
2
8.3 Reading from a port (Input mode)
S A6
START condition
slave address
t
3
v(D)
4
All ports programmed as input should be set to logic 1. To read, the master
(microcontroller) first addresses the slave device after it receives the interrupt. By setting
the last bit of the byte containing the slave address to logic 1 the Read mode is entered.
The data bytes that follow on the SDA are the values on the ports.
If the data on the input port changes faster than the master can read, this data may be
lost.
A5 A4 A3 A2 A1 A0 1
5
slave address
6
7
R/W
8
9
A
acknowledge
from slave
t
h(D)
P7
R/W
P6 1
A
acknowledge
from slave
P5
Rev. 05 — 15 June 2009
t
P4 P3 P2 P1 P0
data 1
d(rst)
DATA 2
Remote 8-bit I/O expander for Fm+ I
data from port
DATA 1
DATA 3
I
t
trt(pu)
d(rst)
t
su(D)
A
acknowledge
from slave
P7
t
v(Q)
P6
I
OH
A
acknowledge
from master
0
P5
DATA 1 VALID
t
P4 P3 P2 P1 P0
data 2
d(rst)
data from port
DATA 4
DATA 4
PCA9674/74A
A
acknowledge
from slave
2
C-bus with interrupt
DATA 2 VALID
t
© NXP B.V. 2009. All rights reserved.
v(Q)
1
no acknowledge
from master
002aae524
002aae525
P
STOP
condition
14 of 32