CAT9534YI-GT2 ON Semiconductor, CAT9534YI-GT2 Datasheet - Page 8

• Manufacturer Part Number: CAT9534YI-GT2
• Description: IC I/O EXPANDER I2C 8B 16TSSOP
• Manufacturer: ON Semiconductor

Specifications of CAT9534YI-GT2

• Interface: I²C, SMBus
• Number Of I /o: 8
• Interrupt Output: Yes
• Frequency - Clock: 400kHz
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Includes: POR
• Logic Family: CAT9534
• Operating Supply Voltage: 2.3 V to 5.5 V
• Power Dissipation: 1 W
• Operating Temperature Range: - 40 C to + 85 C
• Input Voltage: 5 V
• Logic Type: I2C, SMBus
• Maximum Clock Frequency: 400 KHz
• Mounting Style: SMD/SMT
• Output Current: 50 mA
• Output Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: CAT9534YI-GT2TR

CAT9534
FUNCTIONAL DESCRIPTION
CAT9534’s general purpose input/ output (GPIO)
peripherals provide up to eight I/O ports, controlled
through an I²C compatible serial interface
The CAT9534 supports the I²C Bus data transmission
protocol. This I²C Bus protocol defines any device that
sends data to the bus to be a transmitter and any
device receiving data to be a receiver. The transfer is
controlled by the Master device which generates the
serial clock and all START and STOP conditions for
bus access. The CAT9534 operates as a Slave
device. Both the Master device and Slave device can
operate as either transmitter or receiver, but the
Master device controls which mode is activated.
I²C BUS PROTOCOL
The features of the I²C bus protocol are defined as
follows:
(1) Data transfer may be initiated only when the bus
(2) During a data transfer, the data line must remain
START AND STOP CONDITIONS
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
Doc. No. MD-9004 Rev. D
is not busy.
stable whenever the clock line is high. Any
changes in the data line while the clock line is
high will be interpreted as a START or STOP
condition (Figure 5).
SDA
SCL
CONDITION
START
0
Figure 6. CAT9534 Slave Address
Figure 5. START/STOP Condition
1
FIXED
SLAVE ADDRESS
0
0
8
PROGRAMMABLE
A2
SDA when SCL is HIGH. The CAT9534 monitors the
SDA and SCL lines and will not respond until this
condition is met.
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must
end with a STOP condition.
DEVICE ADDRESSING
After the bus Master sends a START condition, a slave
address byte is required to enable the CAT9534 for a
read or write operation. The four most significant bits of
the slave address are fixed as binary 0100 and the next
three bits are its individual address bits (Figure 6).
The address bits A2, A1 and A0 are used to select
which device is accessed from maximum eight
devices on the same bus. These bits must compare to
their hardwired input pins. The 8th bit following the 7-
bit slave address is the R/W ¯ ¯ bit that specifies whether
a read or write operation is to be performed. When
this bit is set to “1”, a read operation is initiated, and
when set to “0”, a write operation is selected.
Following the START condition and the slave address
byte, the CAT9534 monitors the bus and responds with
an acknowledge (on the SDA line) when its address
matches the transmitted slave address. The CAT9534
then performs a read or a write operation depending on
the state of the R/W ¯ ¯ bit.
SELECTABLE
HARDWARE
A1
A0
R/W
CONDITION
STOP
Characteristics subject to change without notice
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