CAT9534YI-GT2 ON Semiconductor, CAT9534YI-GT2 Datasheet - Page 11

IC I/O EXPANDER I2C 8B 16TSSOP

CAT9534YI-GT2

Manufacturer Part Number
CAT9534YI-GT2
Description
IC I/O EXPANDER I2C 8B 16TSSOP
Manufacturer
ON Semiconductor
Datasheet

Specifications of CAT9534YI-GT2

Interface
I²C, SMBus
Number Of I /o
8
Interrupt Output
Yes
Frequency - Clock
400kHz
Voltage - Supply
2.3 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-TSSOP
Includes
POR
Logic Family
CAT9534
Operating Supply Voltage
2.3 V to 5.5 V
Power Dissipation
1 W
Operating Temperature Range
- 40 C to + 85 C
Input Voltage
5 V
Logic Type
I2C, SMBus
Maximum Clock Frequency
400 KHz
Mounting Style
SMD/SMT
Output Current
50 mA
Output Voltage
5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
CAT9534YI-GT2TR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CAT9534YI-GT2
Manufacturer:
ON Semiconductor
Quantity:
1 150
INTERRUPT OUTPUT
CAT9534’s interrupt otuput is an active LOW open-
drain output that is activated when any port pin
configured as an input changes state. The interrupt
output is reset when the input returns to its previous
state or the Input Port Register is read.
Note that changing an I/O from an output to an input
may cause a false interrupt to occur if the state of
the pin does not match the contents of the Input Port
register.
READ FROM
© 2010 SCILLC. All rights reserved
Characteristics subject to change without notice
S
DATA INTO
0
PORT
PORT
SDA
SCL
INT
1
slave address
acknowledge from slave
0
t
start condition
IV
S
0 A2
1
0
2
A1
1
slave address
3
A0
0
R/W
4
0
0
A2
5
DATA 1
A
acknowledge
A1
6
from slave
A0
7
COMMAND BYTE
t
acknowledge from slave
PH
t
IR
R/W
8
1
Figure 11. Read Input Port Register
Figure 10. Read from Register
9
A
DATA 2
At this moment master-transmitter becomes
data from port
A
master-receiver and slave-receiver
DATA 1
11
S
DATA 3
0
acknowledge
becomes slave-transmitter
POWER-ON RESET OPERATION
When the power supply is applied to V
internal power-on reset pulse holds the CAT9534 in
a reset state until V
point, the reset condition is released and the internal
state machine and the CAT9534’s registers are
initialized to their default state.
from master
t
PS
1
slave address
acknowledge from slave
0
0
A2 A1 A0
A
R/W
1
CC
A
data from port
reaches V
DATA 4
data from register
DATA 4
no acknowledge
data from register
last byte
from master
DATA
no acknowledge
first byte
POR
DATA
from master
Doc. No. MD-9004 Rev. D
acknowledge
from master
level. At this
CC
NA
CAT9534
pin, an
stop
condition
NA
P
A
P

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