PCF8575CTS/1,112 NXP Semiconductors, PCF8575CTS/1,112 Datasheet - Page 11

• Manufacturer Part Number: PCF8575CTS/1,112
• Description: IC I/O EXPANDER I2C 16B 24SSOP
• Manufacturer: NXP Semiconductors

Specifications of PCF8575CTS/1,112

• Interface: I²C
• Number Of I /o: 16
• Interrupt Output: Yes
• Frequency - Clock: 400kHz
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP
• Includes: POR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3528-5; 935278677112; PCF8575CTSDB

Philips Semiconductors
7
The I
between different ICs or modules. The two lines are a
serial data line (SDA) and a serial clock line (SCL). Both
lines must be connected to a positive supply via a pull-up
resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not
busy.
7.1
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during the HIGH
period of the clock pulse as changes in the data line at this
time will be interpreted as control signals (see Fig.9).
7.2
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH is defined as the STOP condition P (see Fig.10).
7.3
A device generating a message is a ‘transmitter’, a device
receiving the message is the ‘receiver’. The device that
controls the message is the ‘master’ and the devices which
are controlled by the master are the ‘slaves’ (see Fig.11).
1999 Aug 05
handbook, full pagewidth
Remote 16-bit I/O expander for I
CHARACTERISTICS OF THE I
2
C-bus is for bidirectional, 2-line communication
Bit transfer
START and STOP conditions
System configuration
SDA
SCL
2
C-BUS
data valid
data line
stable;
Fig.9 Bit transfer.
2
C-bus
11
allowed
change
of data
7.4
The number of data bytes transferred between the START
and the STOP conditions from transmitter to receiver is not
limited. Each byte of eight bits is followed by one
acknowledge bit. The transmitter must release the SDA
line before the receiver can send an acknowledge bit.
A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. Also a
master must generate an acknowledge after the reception
of each byte that has been clocked out of the slave
transmitter. The device that acknowledges has to pull
down the SDA line during the acknowledge clock pulse, so
that the SDA line is stable LOW during the HIGH period of
the acknowledge related clock pulse, set-up and hold
times must be taken into account.
A master receiver must signal an end of data to the
transmitter by not generating an acknowledge after the
last byte that has been clocked out of the slave. This is
done by the master receiver by holding the SDA line HIGH.
In this event the transmitter must release the data line to
enable the master to generate a STOP condition.
Acknowledge
MBC621
Product specification
PCF8575C