PCA9557PW,112 NXP Semiconductors, PCA9557PW,112 Datasheet - Page 9

• Manufacturer Part Number: PCA9557PW,112
• Description: IC I/O EXPANDER I2C 8B 16TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9557PW,112

• Package / Case: 16-TSSOP
• Interface: I²C, SMBus
• Number Of I /o: 8
• Interrupt Output: No
• Frequency - Clock: 400kHz
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Includes: POR
• Logic Family: PCA
• Operating Supply Voltage: 2.3 V to 5.5 V
• Power Dissipation: 200 mW
• Operating Temperature Range: - 40 C to + 85 C
• Maximum Clock Frequency: 400 KHz
• Mounting Style: SMD/SMT
• Output Current: 50 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-5028; 935270669112; PCA9557PW; PCA9557PW,112; PCA9557PW

NXP Semiconductors
8. Characteristics of the I
PCA9557
Product data sheet
8.1.1 START and STOP conditions
7.4 Power-on reset
7.5 RESET input
8.1 Bit transfer
When power is applied to V
a reset condition until V
and the PCA9557 registers and I
states. Thereafter, V
A reset can be accomplished by holding the RESET pin LOW for a minimum of t
PCA9557 registers and SMBus/I
until the RESET input is once again HIGH. This input requires a pull-up resistor to V
no active connection is used.
The I
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see
Fig 10. Bit transfer
2
C-bus is for 2-way, 2-line communication between different ICs or modules. The two
2
SDA
SCL
Figure
C-bus
DD
Rev. 06 — 11 June 2008
DD
must be lowered below 0.2 V to reset the device.
11).
has reached V
DD
, an internal Power-On Reset (POR) holds the PCA9557 in
2
2
C-bus/SMBus state machine will initialize to their default
C-bus state machine will be held in their default state
data valid
data line
stable;
POR
Figure
8-bit I
. At that point, the reset condition is released
allowed
change
of data
10).
2
C-bus and SMBus I/O port with reset
mba607
PCA9557
© NXP B.V. 2008. All rights reserved.
w(rst)
. The
DD
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if