PCA9557D,112 NXP Semiconductors, PCA9557D,112 Datasheet - Page 8

• Manufacturer Part Number: PCA9557D,112
• Description: IC I/O EXPANDER I2C 8B 16SOIC
• Manufacturer: NXP Semiconductors

Specifications of PCA9557D,112

• Package / Case: 16-SOIC (3.9mm Width)
• Interface: I²C, SMBus
• Number Of I /o: 8
• Interrupt Output: No
• Frequency - Clock: 400kHz
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Includes: POR
• Logic Family: PCA9557
• Number Of Lines (input / Output): 8.0 / 8.0
• Operating Supply Voltage: 2.3 V to 5.5 V
• Power Dissipation: 200 mW
• Operating Temperature Range: - 40 C to + 85 C
• Input Voltage: 5 V
• Logic Type: I2C, SMBus
• Maximum Clock Frequency: 400 KHz
• Mounting Style: SMD/SMT
• Number Of Input Lines: 8.0
• Number Of Output Lines: 8.0
• Output Current: 50 mA
• Output Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-1060-5; 935270674112; PCA9557D

NXP Semiconductors
PCA9557
Product data sheet
7.3.1 Register 0 - Input port register
7.3.2 Register 1 - Output port register
7.3.3 Register 2 - Polarity inversion register
7.3.4 Register 3 - Configuration register
7.3 Register descriptions
This register is a read-only port. It reflects the incoming logic levels of the pins, regardless
of whether the pin is defined as an input or an output by the Configuration register. Writes
to this register have no effect.
Table 5.
This register reflects the outgoing logic levels of the pins defined as outputs by the
Configuration register. Bit values in this register have no effect on pins defined as inputs.
In turn, reads from this register reflect the value that is in the flip-flop controlling the output
selection, not the actual pin value.
Table 6.
This register enables polarity inversion of pins defined as inputs by the Configuration
register. If a bit in this register is set (written with logic 1), the corresponding port pin’s
polarity is inverted. If a bit in this register is cleared (written with logic 0), the
corresponding port pin’s original polarity is retained.
Table 7.
This register configures the directions of the I/O pins. If a bit in this register is set, the
corresponding port pin is enabled as an input with high-impedance output driver. If a bit in
this register is cleared, the corresponding port pin is enabled as an output.
Table 8.
Bit
Symbol
Bit
Symbol
Default
Bit
Symbol
Default
Bit
Symbol
Default
Register 0 - Input port register bit allocation
Register 1 - Output port register bit allocation
Register 2 - Polarity inversion register bit allocation
Register 3 - Configuration register bit allocation
O7
N7
C7
I7
7
7
0
7
1
7
1
O6
Rev. 06 — 11 June 2008
N6
C6
I6
6
6
0
6
1
6
1
O5
N5
C5
I5
5
5
0
5
1
5
1
O4
N4
C4
8-bit I
I4
4
4
0
4
1
4
1
2
C-bus and SMBus I/O port with reset
O3
N3
C3
I3
3
3
0
3
0
3
1
O2
N2
C2
I2
2
2
2
2
0
0
1
PCA9557
© NXP B.V. 2008. All rights reserved.
O1
N1
C1
I1
1
1
0
1
0
1
1
O0
N0
C0
I0
0
0
0
0
0
0
1
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