PCA9538PW,118 NXP Semiconductors, PCA9538PW,118 Datasheet - Page 9

IC I/O EXPANDER I2C 8B 16TSSOP

PCA9538PW,118

Manufacturer Part Number
PCA9538PW,118
Description
IC I/O EXPANDER I2C 8B 16TSSOP
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PCA9538PW,118

Package / Case
16-TSSOP
Interface
I²C, SMBus
Number Of I /o
8
Interrupt Output
Yes
Frequency - Clock
400kHz
Voltage - Supply
2.3 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Includes
POR
Logic Family
PCA9538
Number Of Lines (input / Output)
8.0 / 8.0
Operating Supply Voltage
2.3 V to 5.5 V
Power Dissipation
200 mW
Operating Temperature Range
- 40 C to + 85 C
Input Voltage
5 V
Logic Type
I2C, SMBus
Maximum Clock Frequency
400 KHz
Mounting Style
SMD/SMT
Number Of Input Lines
8.0
Number Of Output Lines
8.0
Output Current
50 mA
Output Voltage
5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
568-3615 - DEMO BOARD I2C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-1840-2
935277419118
PCA9538PW-T

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PCA9538PW,118
Manufacturer:
TI
Quantity:
2 500
NXP Semiconductors
PCA9538_5
Product data sheet
Fig 7.
Fig 8.
SDA
write to port
data out from port
data to register
Expanded diagram is shown in
Write to output port register
Write to configuration or polarity inversion registers
SCL
SDA
S
SCL
START condition
1
S
START condition
1
6.7 Bus transactions
1
2
1
1
slave address
2
3
1
1
Data is transmitted to the PCA9538 registers using the write mode as shown in
and
Figure 9
once a command byte has been sent, the register which was addressed will continue to
be accessed by reads until a new command byte has been sent.
slave address
3
4
1
0
4
Figure
5
0
0 A1 A0
5
6
0 A1 A0
and
6
7
8. Data is read from the PCA9538 registers using the read mode as shown in
R/W
Figure
7
8
Figure
0
R/W
8
9
0
A
acknowledge
from slave
8-bit I
18.
9
A
acknowledge
from slave
0
10. These devices do not implement an auto-increment function so
0
0
2
Rev. 05 — 28 May 2009
C-bus and SMBus low power I/O port with interrupt and reset
command byte
0
0
command byte
0
0
0
0
0
0
0
0
1 1/0
1
A
acknowledge
from slave
A
acknowledge
from slave
data to port
DATA 1
data to register
DATA 1
t
v(Q)
A
acknowledge
from slave
PCA9538
© NXP B.V. 2009. All rights reserved.
DATA 1 VALID
A
acknowledge
from slave
STOP
condition
P
002aae708
STOP
condition
P
002aae709
Figure 7
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