PCA9536D,118 NXP Semiconductors, PCA9536D,118 Datasheet - Page 12

• Manufacturer Part Number: PCA9536D,118
• Description: IC I/O EXPANDER I2C 4B 8SOIC
• Manufacturer: NXP Semiconductors

Specifications of PCA9536D,118

• Package / Case: 8-SOIC (3.9mm Width)
• Interface: I²C, SMBus
• Number Of I /o: 4
• Interrupt Output: No
• Frequency - Clock: 400kHz
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Includes: POR
• Logic Family: PCA9536
• Number Of Lines (input / Output): 4.0 / 4.0
• Operating Supply Voltage: 2.3 V to 5.5 V
• Power Dissipation: 200 mW
• Operating Temperature Range: - 40 C to + 85 C
• Input Voltage: 5 V
• Logic Type: I2C, SMBus
• Maximum Clock Frequency: 400 KHz
• Mounting Style: SMD/SMT
• Number Of Input Lines: 4.0
• Number Of Output Lines: 4.0
• Output Current: 50 mA
• Output Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-3615 - DEMO BOARD I2C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-1835-2; 935277415118; PCA9536D-T

NXP Semiconductors
10. Dynamic characteristics
Table 10.
[1]
[2]
[3]
PCA9536_5
Product data sheet
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
t
t
Port timing
t
t
t
SCL
BUF
HD;STA
SU;STA
SU;STO
HD;DAT
VD;ACK
VD;DAT
SU;DAT
LOW
HIGH
r
f
SP
v(Q)
su(D)
h(D)
Fig 12. Definition of timing
t
t
C
VD;ACK
VD;DAT
b
= total capacitance of one bus line in pF.
= minimum time for SDA data output to be valid following SCL LOW.
= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
Dynamic characteristics
SDA
SCL
Parameter
SCL clock frequency
bus free time between a STOP and
START condition
hold time (repeated) START condition
set-up time for a repeated START
condition
set-up time for STOP condition
data hold time
data valid acknowledge time
data valid time
data set-up time
LOW period of the SCL clock
HIGH period of the SCL clock
rise time of both SDA and SCL signals
fall time of both SDA and SCL signals
pulse width of spikes that must be
suppressed by the input filter
data output valid time
data input set-up time
data input hold time
t
f
S
t
HD;STA
t
LOW
t
r
t
HD;DAT
t
SU;DAT
t
HIGH
Rev. 05 — 25 January 2010
t
f
t
SU;STA
Conditions
Sr
t
HD;STA
[1]
[2]
Standard-mode
Min
300
250
100
4.7
4.0
4.7
4.0
0.3
4.7
4.0
0
0
1
-
-
-
-
I
2
C-bus
t
SU;STO
t
SP
1000
Max
3.45
4-bit I
100
300
200
50
-
-
-
-
-
-
-
-
-
-
-
t
r
2
P
C-bus and SMBus I/O port
20 + 0.1C
20 + 0.1C
Fast-mode I
t
BUF
Min
100
100
1.3
0.6
0.6
0.6
0.1
1.3
0.6
50
0
0
1
-
-
S
PCA9536
b
b
© NXP B.V. 2010. All rights reserved.
[3]
[3]
002aab271
2
C-bus
Max
400
300
300
200
0.9
50
-
-
-
-
-
-
-
-
-
-
-
12 of 22
ns
ns
ns
Unit
kHz
μs
μs
μs
μs
μs
μs
ns
μs
μs
ns
ns
ns
μs