MAX261BEWG+ Maxim Integrated Products, MAX261BEWG+ Datasheet - Page 15

• Manufacturer Part Number: MAX261BEWG+
• Description: IC FILTER ACT MPU PROG 24-SOIC
• Manufacturer: Maxim Integrated Products

Specifications of MAX261BEWG+

• Filter Type: Universal Switched Capacitor
• Frequency - Cutoff Or Center: 57kHz
• Number Of Filters: 2
• Max-order: 2nd
• Voltage - Supply: 4.74 V ~ 12.6 V, ±2.37 V ~ 6.3 V
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 4. Clock Input Connections
the digital lines should be buffered from the device by
logic gates as shown in Figure 6.
The MAX260/MAX261/MAX262 enters a shutdown/
standby mode when all zeroes are written to the Q
addresses of filter A (Q0
power consumption with ±5V supplies typically drops
to 10mW. When reactivating the filter after shutdown,
allow 2ms to return to full operation.
There are several ways in which the summing amplifier
and integrators in each MAX260/MAX261/MAX262 filter
section can be configured. The four most versatile
interconnections (modes) are selected by writing to
*OSC OUT IS PIN 18 ON MAX261/MAX262
CLK
CLK
CLK
FILTER A
FILTER A
FILTER A
11
11
11
A
A
A
CRYSTAL
R
______________________________________________________________________________________
EXTERNAL CLOCK IN
Filter Operating Modes
(ANY DUTY CYCLE)
C
N.C.
19(18)*
19(18)*
OSC
OUT
OSC
OUT
OSC
OUT
A
–Q6
A
). When shut down,
8
8
N.C.
Shutdown Mode
CLK
OUT
CLK
OUT
CLK
OUT
FILTER B
12
FILTER B
FILTER B
12
12
CLK
CLK
CLK
f
Microprocessor Programmable
CLK
B
B
B
= 0.45
RC
Universal Active Filters
inputs M0 and M1 (see Tables 4 and 5). These modes
use no external components. A fifth mode, 3A, makes
use of an additional op amp (included in the MAX261
and MAX262) and external resistors, but uses the same
internal configuration and is selected with the same
programming code, as mode 3.
Table 4. Program Address Locations
Note: Writing 0 into Q0A–Q6A (address locations 4–7) on filter
A activates shutdown mode. BOTH filter sections deactivate.
Figure 5. Interface Timing
FILTER A
FILTER B
D0, D1
M0
Q0
Q2
Q4
Q6
M0
Q0
Q2
Q4
Q6
A0–A3
F0
F2
F4
F0
F2
F4
D0
WR
DATA BIT
A
A
A
B
B
B
A
A
A
A
A
B
B
B
B
B
M1
Q1
Q3
Q5
M1
Q1
Q3
Q5
F1
F3
F5
F1
F3
F5
D1
SEE INTERFACE SPECIFICATIONS FOR TIMING LIMITS
A
A
A
B
B
B
A
A
A
A
B
B
B
B
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
VALID ADDRESS
t
AS
t
WR
ADDRESS
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
VALID DATA
t
DS
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
t
AH
t
DH
LOCATION
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
15