STV5348 STMicroelectronics, STV5348 Datasheet - Page 13

• Manufacturer Part Number: STV5348
• Description: IC DECODER TELETEXT/VPS 28-PDIP
• Manufacturer: STMicroelectronics
• Type: Video Decoderr

Specifications of STV5348

• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Mounting Type: Through Hole
• Package / Case: 28-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Voltage - Supply, Analog: -

Table 12. Registers Functions
Register
Address
Address
Address
Address
Address
00H
01H
02H
03H
04H
R0
R1
R2
R3
R4
R11 addressing and
pin functions control
Data relative to the
Selection of one of
Operating mode
requested page
a page request
information for
(see Table 10)
eight pages to
Addressing
Function
controls
display
7 bits + parity or 8 bits
X/24 POSITION (D7)
DISABLE ROLLING
DEW / FULLFIELD
without parity (D6)
T1 (D1)
FREE RUNNING
EVEN OFF (D2)
A0, A1 (D4, D5)
SC0, SC1, SC2
ON / OFF (D5)
ACQUISITION
SEL 11B (D0)
GHOST ROW
ENABLE (D4)
PRD0 - PRD4
TCS ON (D2)
0
0
1
1
(D0, D1, D2)
(D0, D1, D2)
A0, A1, A2
HEADER
(D0 - D4)
PLL (D6)
TB (D3)
A2 (D6)
Bit(s)
(D3)
T0 (D0)
0
1
0
1
Selection of register 11B (D0 = 1) or 11A (D0 = 0)
Control of ODD/EVEN pin: EVEN signal output
(D2 = 0) or grounded (D2 = 1)
D4 = 1, Disable rolling header
D4 = 0, Normal operation
D6 = 0, PLL locks on line frequency
D6 = 1, to force free running mode
D7 = 0, packet X/24 stored to chapter 4 to 7/row 20
D7 = 1, packet X/24 stored to chapter 0 to 3/row 24
Character display line control:
312.5/312.5 line MIX - mode with interlace
312/313 line TEXT - mode without interlace
312/312 line Terminal mode without interlace
External synchronization. SCS mode (scan field
synchro)
Master Mode (MA/SL Pin 2 = 0)
case POL Pin 4 = 0
D2 = 0, Pin 5 = VCS
D2 = 1, Pin 5 = TCS
Slave Mode (MA/SL Pin 2 = V
No effect
Selection of field flyback mode or full channel mode
(D3 = 1) for recovering of Teletext data.
Selection of ghost row mode (D4 = 1)
Control of acquisition operation (D5 = 0 enables
acquisition)
Selection of received data format either 7 bits with
parity (D6 = 0) or 8 bits without parity (D6 = 1).
Address the first column of the on chip page request
RAM to be written.
Test bit equal to "0" in the normal working mode.
Address a group of four consecutive pages currently
used for data acquisition.
Address of one of the two groups of four pages for
acquisition in normal mode.
Written data in the page request RAM, starting with
the columns addressed by SC0, SC1, SC2.
Chapter selection.
Description
DD
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STV5348
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