Z8622912PSG Zilog, Z8622912PSG Datasheet - Page 31

• Manufacturer Part Number: Z8622912PSG
• Description: IC CCD W/2ND I2C ADD 18-DIP
• Manufacturer: Zilog
• Type: Video Decoderr

Specifications of Z8622912PSG

• Applications: Set-Top Boxes, TV
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Mounting Type: Through Hole
• Package / Case: 18-DIP (0.300", 7.62mm)
• Processor Series: Z8622x
• Core: Z80
• Data Bus Width: 8 bit
• Program Memory Type: CGROM
• Program Memory Size: 3.7 B
• Maximum Clock Frequency: 12 MHz
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -
• Lead Free Status / Rohs Status: Details

ZiLOG
Note:
D
mode in the OSD and XDS displays (High = DROP SHAD-
OW and Low = BOX). The default is High.
D
acter row in the OSD and XDS display modes (High = 15
lines/row and Low = 13 lines/row). The default is High.
H Position Register Address = 02h
D0–D5–h0–h5.
of the display. The default value in this register is 26h. Each
count change represents an incremental timing change of
330 ns. Decreasing the value of this field moves the display
to the RIGHT. Conversely, increasing the value of this field
moves the display to the LEFT.
D
the HIN signal when in the EXT HLK mode (Low = Rising
Edge, High = Falling Edge). The default is Low.
D
Blue Box and Low = Black Box). The default is Low.
Text Position Register Address = 03h
D
display. The default is 15 rows.
D
play.
The default value in this register is set to FFh, which pro-
duces a 15-row display with base row 15. Entering a new
value in this register can alter the size and placement of the
Text display. For example, to produce an 8-row Text display
Bit
Bit
6
7
6
7
0
4
–ODRP.
–O15.
–HPO.
–BLUBX.
–D
–D
Figure 22. Text Position Register (Address = 03h)
BLUBX HPO
R/W
Figure 21. H Position Register (Address = 02h)
R/W
D
3
7
OSD and XDS display modes always have Enhanced At-
y
D
tributes enabled.
–x
–y
7
3
7
0
0
This bit selects the number of TV lines per char-
–x
–y
This bit sets the polarity to be used for locking to
R/W
This bit selects the Drop Shadow or Full Box
R/W
D
y
3
3
This bit designates the color of BOX (High =
D
6
.
.
2
6
This bit sets the Number Of Rows in the Text
This bit sets the Base Row of the Text dis-
This bit is used to set the Horizontal Timing
R/W
R/W
D
y
D
h
5
1
5
5
R/W
R/W
D
y
D
h
0
4
4
4
R/W
R/W
D
D
x
h
3
3
3
3
R/W
R/W
D
x
D
h
2
2
2
2
R/W
R/W
D
D
x
h
1
1
1
1
R/W
R/W
D
D
x
h
0
0
0
0
with a base row of 12, this register should be set to C8h. If
the value of the
rows are off the top of the screen, then the first row of the
Text display starts in row 1, having the number of rows de-
termined by the
Line 21 Activity Register Address = 04h
D
Channel selected for display. The display becomes inactive
if no data is received for the selected channel within the pre-
vious 16 seconds (High = Active, Low = Inactive). The reset
state is Low.
D
cessed. The display becomes inactive if no XDS data is re-
ceived within the previous 16 seconds (High = Active, Low
= Inactive). The reset state is Low.
D
XDS Filter Register Address = 05h
D
output through the Serial Control port when XDS recovery
has been enabled.
D
put through the Serial Control port when XDS recovery has
been enabled.
D
packets for output through the Serial Control port when
XDS recovery has been enabled.
D
for output through the Serial Control port when XDS re-
covery has been enabled.
Bit
Bit
0
1
2
0
1
2
3
Figure 23. Line 21 Activity Register (Address = 04h)
–SCH.
–XDS.
–D
–CURR.
–FUTR.
–CHAN.
–MISC.
R/W
Figure 24. XDS Filter Register (Address = 05h)
7
D
res
D
s
.
2
7
7
Reserved.
This bit indicates data being processed in the Data
This bit indicates that XDS data is being pro-
This bit selects the Miscellaneous Class packets
This bit selects the Future Class packets for out-
R/W
This bit selects the Channel Information Class
This bit selects the Current Class packets for
D
D
res
s
6
1
6
x
x
and
value.
R/W
D
res
D
s
0
5
5
y
bits result in a display where Text
PUBL
R/W
D
res
D
4
4
MISC CHAN FUTR CURR
R/W
D
res
D
3
3
R/W
D
D
res
2
2
XDS
R/W
D
D
R
1
1
SCH
R/W
D
R
D
0
0