Z8622912PSG Zilog, Z8622912PSG Datasheet - Page 25

• Manufacturer Part Number: Z8622912PSG
• Description: IC CCD W/2ND I2C ADD 18-DIP
• Manufacturer: Zilog
• Type: Video Decoderr

Specifications of Z8622912PSG

• Applications: Set-Top Boxes, TV
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Mounting Type: Through Hole
• Package / Case: 18-DIP (0.300", 7.62mm)
• Processor Series: Z8622x
• Core: Z80
• Data Bus Width: 8 bit
• Program Memory Type: CGROM
• Program Memory Size: 3.7 B
• Maximum Clock Frequency: 12 MHz
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -
• Lead Free Status / Rohs Status: Details

ZiLOG
A command string can be interrupted at any time. The port
is resynchronized by sending the Serial Sync signal or by
activating the rising edge of SEN.
The SPI bus is a three-wire bus when used in a dedicated
manner between the Z86229 and the master device. If other
peripherals are connected to the bus, then the SEN pin must
be used to place this device on the bus at the appropriate
time. When SEN is Low, the SDO pin becomes tri-stated,
transitioning on the SCK and SDA pins, which, as a result,
are ignored.
If data output is not required from the Z86229, then control
can be accomplished using only the SCK and SDA pins. Be-
cause this type of operation precludes the ability to check
the RDY bit, it is very important that commands be spaced
by at least two frames (66 msec) to ensure that one command
has been executed before initiating another.
The bus is controlled by the master device, which generates
the serial clock (SCK) and initiates all actions. Clocking
data in on the SDA simultaneously produces a data out on
the SDO. The master should always check for the appro-
priate handshake signal before executing any command oth-
er than a NOP.
Writing to the part requires that the RDY bit be set, while
reading from the part requires checking the SS register to
see if the DAV bit is set. Both of these bits are contained
in the Serial Status (SS) register. Writing to the Z86229 con-
currently outputs the contents of the SS register, MSB first,
unless other data is being output as a result of one of the
READ commands. If it is required to read the SS without
executing a command, the NOP command can be written
at any time, even if the serial status RDY bit is not set.
The RDY status bit is driven onto the SDO pin between
command transmissions. The controlling MCU can test the
state of this pin, without clocking, in order to determine if
subsequent serial transfers are possible. The DAV bit can
only be checked by outputting the contents of the SS reg-
ister.
Writing to the SPI Bus
All write commands are either one or two-byte commands.
The number of data bytes to be received by the Z86229 is
inherent in the command. If the master device writes more
bytes than expected, the command may be overwritten or
corrupted by the extraneous bytes.
A write to the Z86229 should always be preceded by exe-
cuting a Status read to verify that the device is ready. The
serial status is output by the device, concurrent with the in-
put of any command byte. If the RDY bit of the serial status
register is set, the master device can write a new command.
The command and data bytes are written MSB first. Typi-
cally, the first byte of a two-byte command is sent first. The
bits are clocked into the Z86229 by placing the data on the
SDA input and bringing the SCK High.
Reading Data Using the SPI Bus
With the exception of the SS read, each read operation must
be set up before the data can actually be read from the serial
output registers of the device. Data is set up for a read op-
eration either automatically or manually. The XDS data is
set up for a READ automatically upon recovery by setting
a valid XDS FILTER register selection. All other data read
operations must be set up manually, using the READ SE-
LECT commands RDS1 and RDS2. These commands load
the selected data byte( or pair of bytes) into the serial output
registers, set the SS register RD2 bit according to the num-
ber of data bytes requested, and set the serial status DAV
bit to indicate the availability of data.
The Z86229 SPI Bus supports two and three byte read se-
quences. In SPI mode, the SS must be read before a read
sequence is started, so that the DAV and RD2 bits can be
checked. The number of data bytes available is indicated by
the state of the RD2 bit. The special command, READ1 or
READ2, is then used to read the one or two available data
bytes. The serial status is clocked out during the write of
the READ1 or READ2 command. The data byte or bytes
are then clocked-out in sequence, MSB first, while the NOP
commands are written into the device. Data bits are clocked-
out on the rising edge of SCK. All available data bytes must
be read to clear the DAV bit and permit subsequent reads.
The SPI Bus Protocol
The SPI Bus Protocol is defined as follows:
1. The first bit of the first output byte is driven out on the
2. A three-wire bus is defined with a Clock signal on the
3. The SEN pin Low disables the port, placing the SDO
4. The SEN pin High enables the port for operation.
5. The SEN and SMS pins Low indicate a hardware reset
6. Serial synchronization can be established by clocking
SDO. This action is followed by the rising edge of
SCK on the last bit (LSB) of the READ1 or READ2
command.
SCK pin, a Serial Data Input on the SDA pin, and a
Serial Data Output on the SDO pin.
pin in a tri-state. Signal transitions on SCK and SDA
are ignored.
for the part. These pins must be held Low for at least
100 ns.
in the minimum required SSR string of FFh, FFh, FEh.
More than two bytes of FFh may be input, but the
string must end with FEh.