ADV7301AKST Analog Devices Inc, ADV7301AKST Datasheet - Page 30

• Manufacturer Part Number: ADV7301AKST
• Description: IC DAC VIDEO HDTV 6-12BIT 64LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of ADV7301AKST

• Rohs Status: RoHS non-compliant
• Applications: DVD, Set-Top Boxes
• Voltage - Supply, Analog: 2.37 V ~ 2.63 V
• Voltage - Supply, Digital: 2.37 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Number Of Dac's: 6
• Adc/dac Resolution: 12b
• Screening Level: Commercial
• Package Type: LQFP
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

ADV7300A/ADV7301A
PROGRESSIVE SCAN AT 27 MHz OR 54 MHz
YCrCb progressive scan data can be input at 27 MHz or 54 MHz.
The input data is interleaved onto a single 10-bit bus and is input
on Pins Y9–Y0. For PS Input Only Mode, the input clock
must be input on CLKIN_A. In Simultaneous SD/HD Mode,
the input clock is input on CLKIN_B.
When the input sequence of the PS data, i.e., 10-bit interleaved
at 27 MHz, starts with Y0 data, as shown in Figure 26, PIXEL
ALIGN [Subaddress 01h] must be set to “0.” In this case, the
timing information embedded in the data stream is recognized
and the video data is transferred to the according Y channel
and CrCb channel processing blocks.
Figure 25. 1
PROGRESSIVE
DECODER
INTERLACED
MPEG2
YCrCb
TO
10-Bit PS @ 27 MHz or 54 MHz
27MHz OR
YCrCb
54MHz
10
3
CLKIN_A
Y9–Y0
P_VSYNC
P_HSYNC
P_BLANK
ADV7300A/
ADV7301A
–30–
If the input sequence starts with Cb0 data as shown in Figure 27,
initially PIXEL ALIGN [Subaddress 01h] must be set to “0.”
This ensures that the ADV7300A/ADV7301A locks to the
input sequence in decoding the embedded timing information
correctly. For correct color decoding, the Pixel Align Bit
[Subaddress 01h] must then be set to “l” after a delay of one
field. The ADV7300A/ADV7301A is now in free run mode;
any changes in the timing information are ignored.
PS 10-bit interleaved at 54 MHz must be input with separate
timing signals. EAV/SAV codes cannot be used in this mode.
PIXEL INPUT
PIXEL INPUT
Figure 27. Input Sequence in PS 10-Bit
Interleaved Mode, EAV/SAV Followed by Cb0 Data
CLKIN_A
CLKIN_A
Figure 26. Input Sequence in PS 10-Bit
Interleaved Mode, EAV/SAV Followed by Y0 Data
DATA
DATA
3FF
3FF
00
00
00
00
XY
XY
Cb0
Y0
Cb0
Y0
Cr0
Y1
REV. A
Cr0
Y1