ADV7188BSTZ Analog Devices Inc, ADV7188BSTZ Datasheet - Page 78

• Manufacturer Part Number: ADV7188BSTZ
• Description: IC DECODER VID MULTIFORM 80LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7188BSTZ

• Applications: Set-Top Boxes, Video Players, Recorders
• Voltage - Supply, Analog: 3.15 V ~ 3.45 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Resolution (bits): 12bit
• Input Format: Analog
• Output Format: Digital
• Adc Sample Rate: 54MSPS
• No. Of Input Channels: 12
• Supply Voltage Range: 3V To 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADV7188
Interrupt Request Output Operation
When an interrupt event occurs, the interrupt pin
INTRQ goes low, with a programmable duration given
by INTRQ_DUR_SEL [1:0]
INTRQ_DUR_SEL [1:0], Interrupt Duration Select,
Address 0x40 [7:6], User Sub Map
Table 98. INTRQ_DUR_SEL [1:0] Function
INTRQ_DUR_SEL [1:0]
00 (default)
01
10
11
When the active-until-cleared interrupt duration is selected and the
event that caused the interrupt is no longer in force, the interrupt
persists until it is masked or cleared.
For example, if the ADV7188 loses lock, an interrupt is generated
and the INTRQ pin goes low. If the ADV7188 returns to the
locked state, INTRQ continues to be driven low until the
SD_LOCK bit is either masked or cleared.
Interrupt Drive Level
The ADV7188 resets with open drain enabled and interrupt
masking disabled. Therefore, INTRQ is in a high imped-
ance state after a reset. Either 01 or 10 must be written to
INTRQ_OP_SEL [1:0] for a logic level to be driven out from
the INTRQ pin.
It is also possible to write to a bit in the ADV7188 that manually
asserts the INTRQ pin. This bit is MPU_STIM_INTRQ.
Description
3 XTAL periods
15 XTAL periods
63 XTAL periods
Active until cleared
Rev. A | Page 78 of 112
INTRQ_OP_SEL [1:0], Interrupt Duration Select,
Address 0x40 [1:0], User Sub Map
Table 99. INTRQ_OP_SEL [1:0] Function
INTRQ_OP_SEL [1:0]
00 (default)
01
10
11
Multiple Interrupt Events
If an interrupt event occurs and then another interrupt event
occurs before the system controller has cleared or masked the
first interrupt event, the ADV7188 does not generate a second
interrupt signal. Therefore, the system controller should check
all unmasked interrupt status bits because more than one may
be active.
Macrovision Interrupt Selection Bits
The user can select between pseudosync pulse and color stripe
detection as outlined in Table 100.
MV_INTRQ_SEL [1:0], Macrovision Interrupt Selection
Bits, Address 0x40 [5:4], User Sub Map
Table 100. MV_INTRQ_SEL [1:0] Function
MV_INTRQ_SEL [1:0]
00
01 (default)
10
11
Additional information about the interrupt system is detailed in
Table 107.
Description
Reserved
Pseudosync only
Color stripe only
Either pseudosync or color stripe
Description
Open drain
Driven low when active
Driven high when active
Reserved