ADV7189BKSTZ Analog Devices Inc, ADV7189BKSTZ Datasheet - Page 48

• Manufacturer Part Number: ADV7189BKSTZ
• Description: IC DECODER VIDEO W/ADC 80LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7189BKSTZ

• Applications: Set-Top Boxes, Video Players, Recorders
• Voltage - Supply, Analog: 3.15 V ~ 3.45 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Resolution (bits): 12bit
• Input Format: Analog
• Output Format: Digital
• Adc Sample Rate: 54MSPS
• Power Dissipation Pd: 450mW
• No. Of Input Channels: 12
• Supply Voltage Range: 3V To 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADV7189B
SYNC PROCESSING
The ADV7189B has two additional sync processing blocks that
postprocess the raw synchronization information extracted from
the digitized input video. If desired, the blocks can be disabled via
the following two I
ENHSPLL Enable Hsync Processor, Address 0x01[6]
The Hsync processor is designed to filter incoming Hsyncs that
have been corrupted by noise, providing improved performance
for video signals with stable time bases but poor SNR.
Setting ENHSPLL to 0 disables the Hsync processor.
Setting ENHSPLL to 1 (default) enables the Hsync processor.
ENVSPROC Enable Vsync Processor, Address 0x01[3]
This block provides extra filtering of the detected Vsyncs to give
improved vertical lock.
Setting ENVSPROC to 0 disables the Vsync processor.
Setting ENVSPROC to 1 (default) enables the Vsync processor.
VBI DATA DECODE
The following low data rate VBI signals can be decoded by the
ADV7189B:
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•
•
•
•
The presence of any of the above signals is detected and, if
applicable, a parity check is performed. The result of this
testing is contained in a confidence bit in the VBI Info[7:0]
register. Users are encouraged to first examine the VBI Info
register before reading the corresponding data registers. All
VBI data decode bits are read-only.
All VBI data registers are double-buffered with the field sig-
nals. This means that data is extracted from the video lines
and appears in the appropriate I
field transition. They are then static until the next field.
The user should start an I
examining the VBI Info register. Then, depending on what data
was detected, the appropriate data registers should be read.
The data registers are filled with decoded VBI data even if their
corresponding detection bits are low; it is likely that bits within
the decoded data stream are wrong.
The closed captioning data (CCAP) is available in the I
registers, and is also inserted into the output video data
stream during horizontal blanking.
Wide screen signaling (WSS)
Copy generation management systems (CGMS)
Closed captioning (CC)
EDTV
Gemstar 1× and 2× compatible data recovery
2
C bits.
2
C read sequence with VS by first
2
C registers with the next
2
C
Rev. B | Page 48 of 104
The Gemstar-compatible data is not available in the I
registers, and is inserted into the data stream only during
horizontal blanking.
WSSD Wide Screen Signaling Detected, Address 0x90[0]
Logic 1 for this bit indicates the data in the WSS1 and WSS2
registers is valid.
The WSSD bit goes high if the rising edge of the start bit is
detected within a time window, and if the polarity of the parity
bit matches the transmitted data.
When WSSD is 0, no WSS is detected and confidence in the
decoded data is low.
When WSSD is 1, WSS is detected and confidence in the
decoded data is high.
CCAPD Closed Caption Detected, Address 0x90[1]
Logic 1 for this bit indicates the data in the CCAP1 and CCAP2
registers is valid.
The CCAPD bit goes high if the rising edge of the start bit is
detected within a time window, and if the polarity of the parity
bit matches the transmitted data.
When CCAPD is 0, no CCAP signals are detected and
confidence in the decoded data is low.
When CCAPD is 1, the CCAP sequence is detected and
confidence in the decoded data is high.
EDTVD EDTV Sequence Detected, Address 0x90[2]
Logic 1 for this bit indicates the data in the EDTV1, 2, 3
registers is valid.
The EDTVD bit goes high if the rising edge of the start bit is
detected within a time window, and if the polarity of the parity
bit matches the transmitted data.
When EDTVD is 0, no EDTV sequence is detected. Confidence
in decoded data is low.
When EDTVD is 1, an EDTV sequence is detected. Confidence
in decoded data is high.
CGMSD CGMS-A Sequence Detected, Address 0x90[3]
Logic 1 for this bit indicates the data in the CGMS1, 2, 3
registers is valid. The CGMSD bit goes high if a valid CRC
checksum has been calculated from a received CGMS packet.
When CGMSD is 0, no CGMS transmission is detected and
confidence in the decoded data is low.
When CGMSD is 1, the CGMS sequence is decoded and
confidence in the decoded data is high.
2
C