DS26303LN-120+A3 Maxim Integrated Products, DS26303LN-120+A3 Datasheet - Page 77
DS26303LN-120+A3
Manufacturer Part Number
DS26303LN-120+A3
Description
Buffers & Line Drivers 3.3V E1/T1/J1 Short Haul Octal LIU
Manufacturer
Maxim Integrated Products
Datasheet
1.DS26303LN-120A3.pdf
(101 pages)
Specifications of DS26303LN-120+A3
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Table 7-2. ID Code Structure
MSB
Version
Contact Factory
4 bits
Table 7-3 Device ID Codes
DS26303-075
DS26303-125
7.3 Test Registers
IEEE 1149.1 requires a minimum of two test registers: the Bypass Register and the Boundary Scan Register. An
optional test register has been included with the DS26303 design. This test register is the Identification Register
and is used with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller.
7.3.1
This register contains both a shift register path and a latched parallel output for all control cells and digital I/O cells
and is n bits in length.
7.3.2
This is a single 1-bit shift register used with the BYPASS, CLAMP, and HIGHZ instructions that provide a short
path between JTDI and JTDO.
7.3.3
The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register is
selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state. See
7-2
and
PART
Boundary Scan Register
Bypass Register
Identification Register
Table 7-3
for more information about bit usage.
DIE REV
Device ID
16 bits
A1
A1
JTAG REV
0h
0h
JEDEC
00010100001
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
77 of 101
JTAG ID
0080h
0081h
1
LSB
1
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