DS26303LN-120+A3 Maxim Integrated Products, DS26303LN-120+A3 Datasheet - Page 37
DS26303LN-120+A3
Manufacturer Part Number
DS26303LN-120+A3
Description
Buffers & Line Drivers 3.3V E1/T1/J1 Short Haul Octal LIU
Manufacturer
Maxim Integrated Products
Datasheet
1.DS26303LN-120A3.pdf
(101 pages)
Specifications of DS26303LN-120+A3
Lead Free Status / Rohs Status
Details
- Current page: 37 of 101
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: AIS Interrupt Mask Channel n (AISIEn). When this bit is set, interrupts can be generated for LIUn if
AIS status transitions.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: AIS Interrupt Channel n (AISISn). This bit is set when AIS transitions from a 0 to 1 or 1 to 0. The
interupt for LIUn is enabled in AISIE. This bit when latched is cleared by a read operation to the register if
GISC.CWE is reset. This bit when latched is cleared by a write operation to the bit if GISC.CWE is set.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Address Pointer (ADDP). This pointer is used to switch between pointing to the primary registers, the
secondary registers, individual registers, and BERT registers. See
Table 5-12. Address Pointer for Bank Selection
ADDP[7:0] (HEX)
AA
00
01
02
ADDP7
AISIE8
AISIS8
7
0
7
0
7
0
ADDP6
AISIE7
AISIS7
6
0
6
0
6
0
Individual LIU Bank
Secondary Bank
BANK NAME
Primary Bank
AISIE
AIS Interrupt Enable Register
14h
AISIS
AIS Interrupt Status Register
15h
ADDP
Address Pointer for Bank Selection Register
1Fh
BERT Bank
ADDP5
AISIE6
AISIS6
5
0
5
0
5
0
ADDP4
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
AISIE5
AISIS5
37 of 101
4
0
4
0
4
0
ADDP3
AISIE4
AISIS4
Table 5-12
3
0
3
0
3
0
ADDP2
for bank selection.
AISIE3
AISIS3
2
0
2
0
2
0
ADDP1
AISIE2
AISIS2
1
0
1
0
1
0
ADDP0
AISIE1
AISIS1
0
0
0
0
0
0
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