LH7A400N0G000B5 NXP Semiconductors, LH7A400N0G000B5 Datasheet - Page 21

• Manufacturer Part Number: LH7A400N0G000B5
• Description: Microcontrollers (MCU) LCD USB FS/HOST MMU ADC BGA256
• Manufacturer: NXP Semiconductors

Specifications of LH7A400N0G000B5

• Data Bus Width: 32 bit
• Program Memory Type: ROMLess
• Data Ram Size: 80 KB
• Interface Type: IrDA, SCI, SPI, SSP, UART, USB
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: BGA-256
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Details
• Other names: LH7A400N0G000B5;55

32-Bit System-on-Chip
Power Modes
Halt, and Standby. In Run mode, all clocks are hard-
ware-enabled and the processor is clocked. Halt mode
stops the processor clock while waiting for an event
such as a key press, but the device continues to func-
tion. Finally, Standby equates to the computer being
switched ‘off’, i.e. no display (LCD disabled) and the
main oscillator is shut down. The 32.768 kHz oscillator
operates in all three modes.
Reset Modes
resets to the LH7A400; these are nPOR (power on
reset), nPWRFL (power failure) and nURESET (user
reset). If any of these are active, a system reset is gen-
erated internally. A nPOR reset performs a full system
reset. The nPWRFL and nURESET resets will perform
a full system reset except for the SDRAM refresh con-
trol, SDRAM Global Configuration, SDRAM Device
Configuration and the RTC peripheral registers. The
SDRAM controller will issue a self-refresh command to
external SDRAM before the system enters this reset
(the nPWRFL and nURESET resets only, not so for the
nPOR reset). This allows the system to maintain its
Real Time Clock and SDRAM contents. On coming out
of reset, the chip enters Standby mode. Once in Run
mode the PWRSR register can be interrogated to deter-
mine the nature of the reset, and the trigger source,
after which software can then take appropriate actions.
Preliminary data sheet
The LH7A400 has three operational states: Run,
There are three external signals that can generate
14.7456 MHz
MAIN OSC.
32.768 kHz
RTC OSC.
Figure 5. Clock and State Controller Block Diagram
STATE CONTROLLER
DIVIDE REGISTER
Rev. 01 — 16 July 2007
NXP Semiconductors
HCLK
Data Paths
• The AMBA AHB bus
• The AMBA APB bus
• The External Bus Interface
• The LCD AHB bus
• The DMA busses.
AMBA AHB BUS
Advanced High-performance Bus (AMBA AHB) bus is a
high speed 32-bit-wide data bus. The AMBA AHB is for
high-performance, high clock frequency system modules.
are connected to the LH7A400 core processor using
the AHB bus. These include the external and internal
memory interfaces, the LCD registers, palette RAM
and the bridge to the Advanced Peripheral Bus (APB)
interface. The APB Bridge transparently converts the
AHB access into the slower speed APB accesses. All
of the control registers for the APB peripherals are pro-
grammed using the AHB - APB bridge interface. The
main AHB data and address lines are configured using
a multiplexed bus. This removes the need for tri-state
buffers and bus holders, and simplifies bus arbitration.
The data paths in the LH7A400 are:
The Advanced Microprocessor Bus Architecture
Peripherals that have high bandwidth requirements
/2, /4, /8
FCLK
HCLK
(TO PROCESSOR CORE)
PCLKs
LH7A400
LH7A400-4
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