EP7311-CR-90 Cirrus Logic Inc, EP7311-CR-90 Datasheet - Page 48

• Manufacturer Part Number: EP7311-CR-90
• Description: Microcontrollers (MCU) Hi Perf. Low PWR SOC 90MHz
• Manufacturer: Cirrus Logic Inc

Specifications of EP7311-CR-90

• Processor Series: EP73xx
• Core: ARM720T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / Rohs Status: No

EP7311
High-Performance, Low-Power System on Chip
48
Ball Location
M10
M11
M12
M13
M14
M15
M16
N10
N11
N12
N13
N14
N15
N16
P10
P11
P12
P13
P14
P15
P16
M7
M8
M9
N1
N2
N3
N4
N5
N6
N7
N8
N9
P1
P2
P3
P4
P5
P6
P7
P8
P9
R1
R2
R3
R4
R5
R6
Table V. 256-Ball PBGA Ball Listing (Continued)
PE[1]/BOOTSEL[1]
A[23]/DRA[4]
A[20]/DRA[7]
HALFWORD
SSITXFR
SSIRXDA
SSITXDA
DRIVE[1]
nEXTFIQ
ADCCLK
SMPCLK
VSSRTC
RTCOUT
nADCCS
COL[0]
VDDIO
VDDIO
COL[2]
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
RTCIN
Name
FB[0]
D[27]
D[21]
PD[5]
PD[2]
D[29]
D[26]
D[22]
D[23]
D[24]
PD[4]
PD[1]
RTC ground Real time clock ground
Pad ground I/O ground
Pad ground I/O ground
Pad ground I/O ground
Pad ground I/O ground
Pad ground I/O ground
Pad ground I/O ground
Pad ground I/O ground
Pad ground I/O ground
Pad ground I/O ground
Pad ground I/O ground
Pad ground I/O ground
Pad power
Pad power
Pad power
Pad power
Pad power
Pad power
Pad power
Pad power
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
I
I
I
MCP/CODEC/SSI2 frame sync
PWM drive output
PWM feedback input
Keyboard scanner column drive
Data I/O
System byte address / SDRAM address
Digital I/O power, 3.3V
System byte address / SDRAM address
Data I/O
External fast interrupt input
GPIO port E / boot mode select
Digital I/O power, 3.3V
GPIO port D
GPIO port D
MCP/CODEC/SSI2 serial data input
SSI1 ADC serial clock
SSI1 ADC sample clock
Keyboard scanner column drive
Data I/O
Data I/O
Halfword access select output
Data I/O
Data I/O
Real time clock oscillator output
Digital I/O power, 3.3V
Digital I/O power, 3.3V
Digital I/O power, 3.3V
Digital I/O power
Data I/O
Digital I/O power, 3.3V
Real time clock oscillator input
Digital I/O power, 3.3V
GPIO port D
GPIO port D
MCP/CODEC/SSI2 serial data output
SSI1 ADC chip select
Description
©
Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
Ball Location
R10
R11
R12
R13
R14
R15
R16
T10
T11
T12
T13
T14
T15
T16
R7
R8
R9
T1
T2
T3
T4
T5
T6
T7
T8
T9
Table V. 256-Ball PBGA Ball Listing (Continued)
PD[7]/SDQM[1]
PD[6]/SDQM[0]
A[27]/DRA[0]
A[25]/DRA[2]
A[24]/DRA[3]
A[26]/DRA[1]
VDDCORE
SSIRXFR
ADCOUT
VDDRTC
DRIVE[0]
SSICLK
VDDIO
COL[7]
COL[3]
COL[1]
VDDIO
COL[5]
VDDIO
VSSIO
Name
PD[3]
D[30]
FB[1]
D[28]
D[25]
BUZ
Core power Core power, 2.5V
Pad ground I/O ground
RTC power Real time clock power, 2.5V
Pad power
Pad power
Pad power
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
–
I
Buzzer drive output
Digital I/O power, 3.3V
SSI1 ADC serial data output
Keyboard scanner column drive
Keyboard scanner column drive
Keyboard scanner column drive
Data I/O
System byte address / SDRAM address
System byte address / SDRAM address
Digital I/O power, 3.3V
System byte address / SDRAM address
GPIO port D / SDRAM byte lane mask
GPIO port D / SDRAM byte lane mask
GPIO port D
MCP/CODEC/SSI2 serial clock
MCP/CODEC/SSI2 frame sync
PWM drive output
PWM feedback input
Keyboard scanner column drive
Digital I/O power, 3.3V
Data I/O
System byte address / SDRAM address
Data I/O
Description
DS506F1