EP7311-CR-90 Cirrus Logic Inc, EP7311-CR-90 Datasheet - Page 24

• Manufacturer Part Number: EP7311-CR-90
• Description: Microcontrollers (MCU) Hi Perf. Low PWR SOC 90MHz
• Manufacturer: Cirrus Logic Inc

Specifications of EP7311-CR-90

• Processor Series: EP73xx
• Core: ARM720T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / Rohs Status: No

EP7311
High-Performance, Low-Power System on Chip
Static Memory Burst Read Cycle
24
EXPRDY
EXPCLK
WRITE
WORD
WORD
nMWE
nMOE
HALF
nCS
A
D
Note: 1. Four cycles are shown in the above diagram (minimum wait states, 1-0-0-0). This is the maximum number of consecutive
cycles that can be driven. The number of consecutive cycles can be programmed from 2 to 4, inclusively.
2. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at
18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
3. Consecutive reads with sequential access enabled are identical except that the sequential access wait state field is used to
determine the number of wait states, and no idle cycles are inserted between successive non-sequential ROM/expansion
cycles. This improves performance so the SQAEN bit should always be set where possible.
4. Address, Halfword, Word, and Write hold state until next cycle.
t
CSd
t
Ad
t
WRd
t
MOEd
t
t
HWd
WDd
t
Figure 9. Static Memory Burst Read Cycle Timing Measurement
EXs
©
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EXh
Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
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