SI5040-A-GM Silicon Laboratories Inc, SI5040-A-GM Datasheet - Page 44
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SI5040-A-GM
Manufacturer Part Number
SI5040-A-GM
Description
IC TXRX XFP 10GBPS 32MLP
Manufacturer
Silicon Laboratories Inc
Type
Transceiverr
Specifications of SI5040-A-GM
Voltage - Supply
1.8V, 3.3V
Mounting Type
Surface Mount
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Product
RF / Wireless
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Drivers/receivers
-
Protocol
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Si5040
Register 5. RxintStatus (Sticky Bits)
Reset settings = 0000 0000
44
Bit
7
6
5
4
3
2
1
0
Name
Type
Bit
tpErrAlarm
tpSyncLos
sqmAlarm
Reserved
refLOS
Name
fifoErr
LOS
LOL
D7
R
Read returns zero.
Reference Clock LOS Interrupt.
A latched version of the refLOS alarm status bit. An interrupt is generated if interrupts are
enabled (intEnable = 1) and if not masked by the corresponding interrupt mask bit. The
interrupt may be cleared by writing a zero to this bit position or by disabling interrupts.
Loss of Signal Interrupt.
A latched version of the LOS alarm status bit. An interrupt is generated if interrupts are
enabled (intEnable = 1) and if not masked by the corresponding interrupt mask bit. The
interrupt may be cleared by writing a zero to this bit position or by disabling interrupts.
Loss of Lock Interrupt.
A latched version of the LOL alarm status bit. An interrupt is generated if interrupts are
enabled (intEnable = 1) and if not masked by the corresponding interrupt mask bit. The
interrupt may be cleared by writing a zero to this bit position or by disabling interrupts.
Receiver FIFO Error Interrupt.
A latched version of the fifoErr alarm status bit. An interrupt is generated if interrupts are
enabled (intEnable = 1) and if not masked by the corresponding interrupt mask bit. The
interrupt may be cleared by writing a zero to this bit position or by disabling interrupts.
Test Pattern Generator/Checker Alarm Interrupt.
A latched version of the tpErrAlarm status bit. An interrupt is generated if interrupts are
enabled (intEnable = 1) and if not masked by the corresponding interrupt mask bit. The
interrupt may be cleared by writing a zero to this bit position or by disabling interrupts.
Test Pattern Checker Loss of Sync Interrupt.
A latched version of the tpSyncLos alarm status bit. An interrupt is generated if interrupts
are enabled (intEnable = 1) and if not masked by the corresponding interrupt mask bit.
The interrupt may be cleared by writing a zero to this bit position or by disabling inter-
rupts.
Signal Quality Monitor Alarm Interrupt.
A latched version of the sqmAlarm status bit. An interrupt is generated if interrupts are
enabled (intEnable = 1) and if not masked by the corresponding interrupt mask bit. The
interrupt may be cleared by writing a zero to this bit position or by disabling interrupts.
refLOS
R/W
D6
LOS
R/W
D5
Rev. 0.86
LOL
R/W
D4
Function
fifoErr
R/W
D3
tpErrAlarm tpSyncLos
R/W
D2
R/W
D1
sqmAlarm
R/W
D0