CYP15G0101DXB-BBC Cypress Semiconductor Corp, CYP15G0101DXB-BBC Datasheet - Page 18

• Manufacturer Part Number: CYP15G0101DXB-BBC
• Description: IC TXRX HOTLINK 100-LBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: HOTlink II™r
• Type: Transceiverr

Specifications of CYP15G0101DXB-BBC

• Package / Case: 100-LBGA
• Protocol: Fibre Channel
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Product: PHY
• Supply Voltage (min): 3.135 V
• Supply Current: 0.5 A
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: CYP15G0101DX-EVAL - EVAL BRD FOR HOTLINK II
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

Clock/Data Recovery
The extraction of a bit-rate clock and recovery of bits from a
received serial stream is performed by a CDR block within the
receive channel. The clock extraction function is performed by a
high-performance embedded PLL that tracks the frequency of
the transitions in the incoming bit stream and aligns the phase of
the internal bit-rate clock to the transitions in the serial data
stream.
The
half-character-rate (bit-rate  20) reference clock from the
REFCLK input. This REFCLK input is used to
■
■
■
Regardless of the type of signal present, the CDR will attempt to
recover a data stream from it. If the frequency of the recovered
data stream is outside the limits of the range control monitor, the
CDR will switch to track REFCLK instead of the data stream.
Once the CDR output (RXCLK) frequency returns back close to
REFCLK frequency, the CDR input will be switched back to track
the input data stream. In case no data is present at the input, this
switching behavior may result in brief RXCLK frequency
excursions from REFCLK. However, the validity of the input data
stream is indicated by the LFIx output. The frequency of
REFCLK is required to be within  1500 ppm
of the clock that drives the REFCLK input of the remote
transmitter to ensure a lock to the incoming data stream.
For systems using multiple or redundant connections, the LFI
output can be used to select an alternate data stream. When an
LFI indication is detected, external logic can toggle selection of
the IN1 and IN2 inputs through the INSEL input. When a port
switch takes place, it is necessary for the receive PLL to
reacquire the new serial stream and frame to the incoming
character boundaries.
Deserializer/Framer
Each CDR circuit extracts bits from the serial data stream and
clocks these bits into the shifter/framer at the bit-clock rate.
When enabled, the framer examines the data stream, looking for
one or more comma or K28.5 characters at all possible bit
positions. The location of these characters in the data stream are
used to determine the character boundaries of all following
characters.
Document Number: 38-02031 Rev. *L
Notes
21. REFCLK has no phase or frequency relationship with the recovered clock(s) and only acts as a centering reference to reduce clock synchronization time. REFCLK
22. The standard definition of a Comma contains only seven bits. However, since all valid Comma characters within the 8B/10B character set also have the 8th bit as
23. When receive BIST is enabled on a channel, the low-latency framer must not be enabled. The BIST sequence contains an aliased K28.5 framing character, which
ensure that the VCO (within the CDR) is operating at the correct
frequency
reduce PLL acquisition time
limit unlocked frequency excursions of the CDR VCO when
there is no input data present at the selected serial line receiver.
must be within ±1500 ppm (±0.15%) of the remote transmitter’s PLL reference (REFCLK) frequency. Although transmitting to a HOTLink II receiver necessitates the
frequency difference between the transmitter and receiver reference clocks to be within ±1500 ppm, the stability of the crystal needs to be within the limits specified
by the appropriate standard when transmitting to a remote receiver that is compliant to that standard. For example, to be IEEE 802.3z Gigabit Ethernet compliant,
the frequency stability of the crystal needs to be within ±100 ppm.
an inversion of the 7th bit, the compare pattern is extended to a full eight bits to reduce the possibility of a framing error.
would cause the receiver to update its character boundaries incorrectly.
CDR
accepts
a
character-rate
[21]
(bit-rate  10)
of the frequency
or
Framing Character
The
combinations of framing characters to support requirements of
different interfaces. The selection of the framing character is
made through the FRAMCHAR input.
The specific bit combinations of these framing characters are
listed in
selected framing character is detected by the framer, the
boundaries of the characters present in the received data stream
are known.
Table 11. Framing Character Selector
Framer
The framer operates in one of three different modes, as selected
by the RFMODE input. In addition, the framer itself may be
enabled or disabled through the RFEN input. When
RFEN = LOW, the framer is disabled, and no combination of bits
in a received data stream will alter the character boundaries.
When RFEN = HIGH, the framer-mode selected by RFMODE is
enabled.
When RFMODE = LOW, the low-latency framer is selected. This
framer operates by stretching the recovered character clock until
it aligns with the received character boundaries. In this mode, the
framer starts its alignment process on the first detection of the
selected framing character. To reduce the impact on external
circuits that make use of a recovered clock, the clock period is
not stretched by more than two bit-periods in any one clock cycle.
When
(RXRATE = LOW), the output of properly framed characters may
be delayed by up to nine character-clock cycles from the
detection of the selected framing character. When operated with
a half-character-rate output clock (RXRATE = HIGH), the output
of properly framed characters may be delayed by up to 14
character-clock cycles from the detection of the selected framing
character.
FRAMCHAR
MID (Open)
HIGH
LOW
CYP(V)(W)15G0101DXB
operated
Table
[23]
11. When the specific bit combination of the
Character Name
with
Comma+
Comma–
–K28.5
K28.5
Bits Detected in Framer
a
Reserved for test
character-rate
CYW15G0101DXB
CYP15G0101DXB
CYV15G0101DXB
allows
00111110XX
or 11000001XX
0011111010 or
selection
Bits Detected
1100000101
output
Page 18 of 44
of
[22]
clock
two
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