CY7C68000A-56LFXC Cypress Semiconductor Corp, CY7C68000A-56LFXC Datasheet - Page 6

• Manufacturer Part Number: CY7C68000A-56LFXC
• Description: IC USB 2.0 TX2 TXRX 56VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr
• Type: Transceiverr

Specifications of CY7C68000A-56LFXC

• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3685 - KIT DEV EZ-USB NX2LPCY3683 - KIT EZ-USB TX2 DEVELOPMENT
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Pin Descriptions
Table 1. Pin Descriptions
Document #: 38-08052 Rev. *H
QFN VFBGA
Note
1. Unused inputs should not be left floating. Tie either HIGH or LOW as appropriate. Outputs that are three-statable should only be pulled up or down to ensure
10
49
48
46
44
43
41
39
38
37
36
34
33
31
29
27
26
50
12
13
11
4
8
7
9
3
2
signals at power-up and in standby.
H1
H5
H4
H8
H6
H7
G8
G7
G5
G3
G2
G4
E1
D8
G1
E2
A1
B2
B3
B4
B1
F8
F6
F5
F4
F3
F1
AVCC
AVCC
AGND
AGND
DPLUS
DMINUS
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
CLK
Reset
XcvrSelect
TermSelect
Suspend
Name
Output
Power
Power
Power
Power
Type
Input
Input
Input
Input
I/OZ
I/OZ
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Default
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Z
Z
Analog V
Analog V
Analog Ground Connect to ground with as short a path as possible.
Analog Ground Connect to ground with as short a path as possible.
USB DPLUS Signal Connect to the USB DPLUS signal.
USB DMINUS Signal Connect to the USB DMINUS signal.
Bidirectional Data Bus This bidirectional bus is used as the entire data
bus in the 8-bit bidirectional mode or the least significant eight bits in the
16-bit mode. Under the 8-bit unidirectional mode, these bits are used as
inputs for data, selected by the RxValid signal.
Bidirectional Data Bus This bidirectional bus is used as the upper eight
bits of the data bus when in the 16-bit mode, and not used when in the
8-bit bidirectional mode. Under the 8-bit unidirectional mode these bits
are used as outputs for data, selected by the TxValid signal.
Clock This output is used for clocking the receive and transmit parallel
data on the D[15:0] bus.
Active HIGH Reset Resets the entire chip. This pin can be tied to V
through a 0.1-μF capacitor and to GND through a 100 K resistor for a
10-ms RC time constant.
Transceiver Select This signal selects between the Full Speed (FS) and
the High Speed (HS) transceivers:
0: HS transceiver enabled
1: FS transceiver enabled
Termination Select This signal selects between the Full Speed (FS) and
the High Speed (HS) terminations:
0: HS termination
1: FS termination
Suspend Places the CY7C68000A in a mode that draws minimal power
from supplies. Shuts down all blocks not necessary for Suspend/Resume
operations. While suspended, TermSelect must always be in FS mode
to ensure that the 1.5 Kohm pull up on DPLUS remains powered.
0: CY7C68000A circuitry drawing suspend current
1: CY7C68000A circuitry drawing normal current
CC
CC
This signal provides power to the analog section of the chip.
This signal provides power to the analog section of the chip.
Description
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CY7C68000A
Page 6 of 15
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