CYP15G0101DXB-BBXI Cypress Semiconductor Corp, CYP15G0101DXB-BBXI Datasheet - Page 20

• Manufacturer Part Number: CYP15G0101DXB-BBXI
• Description: IC TXRX HOTLINK 100-LBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: HOTlink II™r
• Type: Transceiverr

Specifications of CYP15G0101DXB-BBXI

• Package / Case: 100-LBGA
• Protocol: Fibre Channel
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Product: PHY
• Data Rate: 1500 MBd
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current: 0.51 A
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CYP15G0101DX-EVAL - EVAL BRD FOR HOTLINK II
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

If the number of invalid characters received ever exceeds the
number of valid characters by 16, the receive BIST state
machine aborts the compare operations and resets the LFSR to
the D0.0 state to look for the start of the BIST sequence again.
When the receive paths are configured for REFCLK clocking
(RXCKSEL = LOW), each pass must be preceded by a
16-character Word Sync Sequence to allow output buffer
alignment and management of clock frequency variations. This
is automatically generated by the transmitter when its local
RXCKSEL = LOW.
The BIST state machine requires the characters to be correctly
framed for it to detect the BIST sequence. If the low-latency
framer is enabled (RFMODE = LOW), the framer will misalign to
an aliased framing character within the BIST sequence. If the
alternate-mode multi-byte framer is enabled (RFMODE = HIGH)
and the receiver outputs are clocked relative to a recovered clock
(RXCKSEL  MID), it is necessary to frame the receiver before
BIST is enabled. If the receiver outputs are clocked relative to
REFCLK (RXCKSEL = LOW), the transmitter precedes every
511 character BIST sequence with a 16-character Word Sync
Sequence.
Receive Elasticity Buffer
The receive channel contains an elasticity buffer that is designed
to support multiple clocking modes. This buffer allows data to be
read using an elasticity buffer read-clock that is asynchronous in
both frequency and phase from the elasticity buffer write clock,
or to use a read clock that is frequency coherent but with uncon-
trolled phase relative to the elasticity buffer write clock.
The elasticity buffer is 10 characters deep, and supports a
12-bit-wide data path. It is capable of supporting a decoded
character, three status bits, and a parity bit for each character
present in the buffer. The write clock for this buffer is always the
recovered clock for the read channel.
The read clock for the elasticity buffer can be set to
character-rate REFCLK (RXCKSEL = LOW and DECMODE 
LOW). The write clock for the elasticity buffer is always
recovered clock.
When RXCKSEL = LOW, the receive channel is clocked by
REFCLK. The RXCLK and RXCLKC+ outputs present buffered
and delayed forms of REFCLK. In this mode, the receive
elasticity buffer is enabled. For REFCLK clocking, the elasticity
buffer must be able to insert K28.5 characters and delete framing
characters as appropriate. The elasticity buffer is bypassed
whenever the decoder is bypassed (DECMODE = LOW). When
the decoder and elasticity buffer are bypassed, RXCKSELx must
be set to MID. When RXCKSEL = MID (or open), the receive
channel output register is clocked by the recovered clock.
The insertion of a K28.5 or deletion of a framing character can
occur at any time. However, the actual timing on these insertions
and deletions is controlled in part by the how the transmitter
sends its data. Insertion of a K28.5 character can only occur
when the receiver has a framing character in the elasticity buffer.
Likewise, to delete a framing character, one must also be present
in the elasticity buffer. To prevent an elasticity buffer overflow or
underflow in the receive channel, a minimum density of framing
characters must be present in the received data stream.
Prior to reception of valid data, at least one Word Sync Sequence
(or at least four framing characters) must be received to allow the
Document Number: 38-02031 Rev. *L
receive elasticity buffer to be centered. The elasticity buffer may
also be centered by a device reset operation initiated through the
TRSTZ input. However, following such an event, the
CYP(V)(W)15G0101DXB will normally require a framing event
before it will correctly decode characters.
Receive Modes
The operating mode of the receive path is set through the
RXMODE input. The ‘Reserved for test’ setting (RXMODE = M)
is not allowed, even if the receiver is not being used, as it will
stop normal function of the device. When the decoder is
disabled, the RXMODE setting is ignored as long as it is not a
test mode. These modes determine the RXST status reporting.
The different receive modes are listed in
Table 12. Receive Operating Modes
Power Control
The CYP(V)(W)15G0101DXB supports user control of the
powered up or down state of the transmit and receive channel.
The receive channel is controlled by the RXLE signal and the
values present on the BOE[1:0] bus. The transmit channel is
controlled by the OELE signal and the values present on the
BOE[1:0] bus. If either the transmit or the receive channel is not
used, then powering down the unused channel will save power
and reduce system heat generation. Controlling system power
dissipation will improve the system performance.
Receive Channel
When RXLE = HIGH, the signal on the BOE[0] input directly
controls the power enable for the receive PLL and the analog
circuit. When BOE[0] = HIGH, the receive channel and its analog
circuits are active. When BOE[0] = LOW, the receive channel
and its analog circuits are powered down. When RXLE returns
LOW, the values present on the BOE[1:0] inputs are latched in
the receive channel enable latch. When a disabled receive
channel is re-enabled, the status of the LFI output and data on
the parallel outputs for the receive channel may be indeterminate
for up to 2 ms.
Transmit Channel
When OELE = HIGH, the signals on the BOE[1:0] inputs directly
control the power enables for the serial drivers. When a BOE[1:0]
input is HIGH, the associated serial driver is enabled. When a
BOE[1:0] input is LOW, the associated serial driver is disabled.
When both serial drivers are powered down, the logic in the
entire transmit channel is also powered down. When OELE
returns LOW, the values present on the BOE[1:0] inputs are
latched in the output enable latch.
Device Reset State
When the CYP(V)(W)15G0101DXB is reset by assertion of
TRSTZ, both the transmit enable and receive enable latches are
cleared, and the BIST enable latch is preset. In this state, the
Number
Mode
0
1
2
RX Mode
RXMODE
M
H
L
CYW15G0101DXB
CYP15G0101DXB
CYV15G0101DXB
Status A
Reserved for test
Status B
RXST Status Reporting
Table
12.
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