CY7B9234-270JXCT Cypress Semiconductor Corp, CY7B9234-270JXCT Datasheet - Page 15

• Manufacturer Part Number: CY7B9234-270JXCT
• Description: IC TRANSMITTER HOTLINK 28-PLCC
• Manufacturer: Cypress Semiconductor Corp
• Series: HOTlink™r
• Type: Transmitter and Receiverr

Specifications of CY7B9234-270JXCT

• Package / Case: 28-PLCC
• Protocol: Fibre Channel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Product: PHY
• Supply Voltage (min): 4.5 V
• Supply Current: 0.085 A
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

When the RF pin is asserted HIGH, RDY leaves it normal mode
of operation and is asserted HIGH while the framer searches the
data stream for a K28.5 character. After the framer has synchro-
nized to a K28.5 character, the Receiver will assert the RDY pin
LOW when the K28.5 character is present at the parallel output.
The RDY pin will then resume its normal operation as dictated by
the MODE and BISTEN pins.
The normal operation of the RDY pin in encoded mode is to
signal when parallel data is present at the output pins by pulsing
LOW with a 60% LOW/40% HIGH duty cycle. RDY does not
pulse LOW in a field of K28.5 characters; however, RDY does
pulse LOW for the last K28.5 character in the field or for any
single K28.5. In unencoded mode, the normal operation of the
RDY pin is to signal when any K28.5 is at the parallel output pins.
Document #: 38-02014 Rev. *B
Q0−7,
SC/D,
RVS
CKR
RDY
RF
Q0−7,
SC/D,
RVS
RDY
CKR
INX
SERIAL DATA IN
DATA
±
RDY IS LOW FOR DATA
FALLING EDGE OF CKR
RF LATCHED ON
DATA
DATA
Figure 3. CY7B9334 Receiver Data Pipeline in Encoded Mode
Figure 4. CY7B9334 Framing Operation in Encoded Mode
DATA
RDY IS HIGH WHILE WAITING FOR K28.5
DATA
RDY IS HIGH IN FIELD OF K28.5S
RECEIVER LATENCY= 24 t
K28.5
DATA
DATA BOUNDARY CHANGES
CKR STRETCHES AS
The Transmitter and Receiver parallel interface timing and
functionality can be made to match the timing and functionality
of either an asynchronous FIFO or a clocked FIFO by appropri-
ately connecting signals (See Figure 5). Proper operation of the
FIFO interface depends upon various FIFO-specific access and
response specifications.
The SMPTE HOTLink Transmitter and Receiver serial interface
provides a seamless interface to various types of media. A
minimal number of external components are needed to properly
terminate transmission lines and provide PECL loads. For proper
power supply decoupling, a single 0.01 μF for each device is all
that is required to bypass the VCC and GND pins. Figure 6 illus-
trates a SMPTE HOTLink Transmitter and Receiver interface to
fiber-optic and copper media. More information on interfacing
SMPTE HOTLink to various media can be found in the “HOTLink
Design Considerations” application note.
DATA
B
+ 10 ns
RDY IS LOW FOR LAST K28.5
K28.5
RDY IS LOW
FOR K28.5
K28.5
DATA
DATA
RDY RESUMES
OPERATION
NORMAL
PARALLEL
DATA OUT
CY7B9234
CY7B9334
DATA
Page 15 of 36
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