AD808-622BRRL7 Analog Devices Inc, AD808-622BRRL7 Datasheet
AD808-622BRRL7
Specifications of AD808-622BRRL7
Related parts for AD808-622BRRL7
AD808-622BRRL7 Summary of contents
Page 1
... Device design guarantees that the clock output frequency will drift by less than 20% in the absence of input data transitions. Shorting the damping factor capacitor, C output frequency to the VCO center frequency. The AD808 consumes 400 mW and operates from a single power supply at either + –5.2 V. FUNCTIONAL BLOCK DIAGRAM QUANTIZER ...
Page 2
... AD808–SPECIFICATIONS Parameter QUANTIZER–DC CHARACTERISTICS Input Voltage Range Input Sensitivity, V SENSE Input Overdrive Input Offset Voltage Input Current Input RMS Noise Input Peak-to-Peak Noise QUANTIZER–AC CHARACTERISTICS Upper –3 dB Bandwidth Input Resistance Input Capacitance Pulsewidth Distortion LEVEL DETECT Level Detect Range ...
Page 3
... RECOVERED CLOCK SKEW Figure 2. Setup and Hold Time Model AD808-622BR AD808-622BRRL7 AD808-622BRRL CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD808 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges ...
Page 4
... This is the frequency at which the VCO will oscillate with the loop damping capacitor shorted. D Tracking Range This is the range of input data rates over which the AD808 will remain in lock. Capture Range This is the range of input data rates over which the AD808 will acquire lock. ...
Page 5
... PIN (Pin 13) and NIN (Pin 12) as shown in Figure 4a. This allows very simple capacitive coupling of the signal from the preamp in the AD808 as shown in Figure 3. The internal common-mode potential is a diode drop (ap- proximately 0.8 V) below the positive supply as shown in Figure 4a ...
Page 6
... AD808–Typical Performance Characteristics 90000 80000 70000 60000 50000 40000 30000 20000 10000 SIGNAL DETECT VOLTAGE – mV Figure 5. Signal Detect Voltage vs. R 8.0 7 7.0 6 6.0 5.5 5 4.5 4.0 –40 – TEMPERATURE – C Figure 6. Signal Detect Hysteresis vs. Temperature STATIC PHASE – Degrees Figure 7. Histogram of Static Phase – ...
Page 7
... Traditionally, high speed comparators are plagued by crosstalk between outputs and inputs, often resulting in oscillations when the input signal approaches 10 mV. The AD808 quantizer toggles (4.0 mV sensitivity) at the input without making bit errors. When the input signal is low- ered below 2 mV, circuit performance is dominated by input noise, and not crosstalk ...
Page 8
... AD808 Center Frequency Clamp (Figure 13) An N-channel FET circuit can be used to bring the AD808 VCO center frequency to within 10% of 622 MHz when SDOUT indicates a Loss of Signal (LOS). This effectively re- duces the frequency acquisition time by reducing the frequency error between the VCO frequency and the input data frequency at clamp release. The N-FET can have “ ...
Page 9
... USING THE AD808 Acquisition Time This is the transient time, measured in bit periods, that required for the AD808 to lock onto the input data from its free running state. Ground Planes The use of one ground plane for connections to both analog and digital grounds is recommended. ...
Page 10
... AD808 0.1574 (4.00) 0.1497 (3.80) 0.0098 (0.25) 0.0040 (0.10) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead Small Outline IC Package (R-16A) 0.3937 (10.00) 0.3859 (9.80 0.2440 (6.20 0.2284 (5.80) PIN 1 0.0688 (1.75) 0.0196 (0.50) 0.0532 (1.35) 0.0099 (0.25) 8 0.0500 0.0192 (0.49) 0 SEATING ...
Page 11
–11– ...
Page 12
–12– ...