M95256-WMN3TP/AB STMicroelectronics, M95256-WMN3TP/AB Datasheet - Page 27

• Manufacturer Part Number: M95256-WMN3TP/AB
• Manufacturer: STMicroelectronics

M95256-DR, M95256, M95256-W, M95256-R
7.1
In applications where the bus master might enter a state where all SPI bus inputs/outputs
would be in high impedance at the same time (for example, if the bus master is reset during
the transmission of an instruction), the clock line (C) must be connected to an external pull-
down resistor. Thus, if all inputs/outputs become high impedance, the C line is pulled low
(while the S line is pulled high). This ensures that S and C do not become high at the same
time, and that the t
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
●
●
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in
bus master is in Stand-by mode and not transferring data:
●
●
Figure 18. SPI modes supported
CPOL
0
1
CPOL=0, CPHA=0
CPOL=1, CPHA=1
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
CPHA
0
1
D
Q
C
C
SHCH
MSB
requirement is met. R typical value is 100 k .
Doc ID 12276 Rev 17
Figure
18, is the clock polarity when the
Connecting to the SPI bus
MSB
AI01438B
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