RC48F4400P0TB0EA Micron Technology Inc, RC48F4400P0TB0EA Datasheet - Page 53

• Manufacturer Part Number: RC48F4400P0TB0EA
• Manufacturer: Micron Technology Inc

Specifications of RC48F4400P0TB0EA

• Cell Type: NOR
• Density: 512Mb
• Interface Type: Parallel/Serial
• Boot Type: Bottom
• Address Bus: 25b
• Operating Supply Voltage (typ): 2.5/3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: EZBGA
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 32M
• Supply Current: 31mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Not Compliant

P33-65nm
Figure 20: Synchronous Single-Word Array or Non-array Read Timing
Notes:
1.
2.
Figure 21: Continuous Burst Read, showing an Output Delay Timing
Notes:
1.
2.
Datasheet
53
Address [A]
Data [D/Q]
ADV# [V]
WAIT [T]
WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either
during or one data cycle before valid data.
This diagram illustrates the case in which an n-word burst is initiated to the flash memory array and it is terminated by
CE# deassertion after the first word in the burst.
OE# [G]
WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either
during or one data cycle before valid data.
At the end of Word Line; the delay incurred when a burst access crosses a 16-word boundary and the starting address is
not 4-word boundary aligned. See
page 37
CLK [C]
CE# [E]
Address [A]
Data [D/Q]
ADV# [V]
WAIT [T]
OE# [G]
CLK [C]
CE# [E]
.
for more information
R105
R105
R301
R302
R303
R101
R102
R105
R105
R306
R106
R301
R303
R15
R104
R104
R101
R102
R2
R3
R7
R15
Section 11.1.3, “End of Word Line (EOWL) Considerations” on
R306
R4
R106
R7
R307
R304
R2
R3
R4
R312
R305
R307
R304
R305
R304
R305
R312
R9
R17
R8
R305
R304
Order Number:320003-09
R304
R305
Mar 2010