RC48F4400P0TB0EA Micron Technology Inc, RC48F4400P0TB0EA Datasheet - Page 40

• Manufacturer Part Number: RC48F4400P0TB0EA
• Manufacturer: Micron Technology Inc

Specifications of RC48F4400P0TB0EA

• Cell Type: NOR
• Density: 512Mb
• Interface Type: Parallel/Serial
• Boot Type: Bottom
• Address Bus: 25b
• Operating Supply Voltage (typ): 2.5/3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: EZBGA
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 32M
• Supply Current: 31mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Not Compliant

Table 15: Burst Sequence Word Ordering (Sheet 2 of 2)
11.1.8
11.1.9
11.1.10
11.2
Datasheet
40
14
15
0
1
2
3
4
5
6
7
1
1
1
1
1
1
1
1
1
1
Clock Edge
The Clock Edge (CE) bit selects either a rising (default) or falling clock edge for CLK.
This clock edge is used at the start of a burst cycle, to output synchronous data, and to
assert/deassert WAIT.
Burst Wrap
The Burst Wrap (BW) bit determines whether 4, 8, or 16-word burst length accesses
wrap within the selected word-length boundaries or cross word-length boundaries.
When BW is set, burst wrapping does not occur (default). When BW is cleared, burst
wrapping occurs.
Burst Length
The Burst Length bits (BL[2:0]) selects the linear burst length for all synchronous burst
reads of the flash memory array. The burst lengths are 4-word, 8-word, 16-word, and
continuous word.
Continuous burst accesses are linear only, and do not wrap within any word length
boundaries (see
cycle begins, the device outputs synchronous burst data until it reaches the end of the
“burstable” address space.
One-Time Programmable (OTP) Registers
The device contains 17 one-time programmable (OTP) registers that can be used to
implement system security measures and/or device identification. Each OTP register
can be individually locked.
The first 128-bit OTP Register is comprised of two 64-bit (8-word) segments. The lower
64-bit segment is pre-programmed at the Numonyx factory with a unique 64-bit
number. The other 64-bit segment, as well as the other sixteen 128-bit OTP Registers,
are blank. Users can program these registers as needed. Once programmed, users can
then lock the OTP Register(s) to prevent additional bit programming (see
“OTP Register Map” on page
0-1-2-3
1-2-3-4
2-3-4-5
3-4-5-6
Table 15, “Burst Sequence Word Ordering” on page
7-8-9-10-11-12-13-14
6-7-8-9-10-11-12-13
5-6-7-8-9-10-11-12
4-5-6-7-8-9-10-11
3-4-5-6-7-8-9-10
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-8
2-3-4-5-6-7-8-9
41).
14-15-16-17-18…28-29
15-16-17-18-19…29-30
7-8-9-10-11…21-22
6-7-8-9-10…20-21
0-1-2-3-4…14-15
1-2-3-4-5…15-16
2-3-4-5-6…16-17
3-4-5-6-7…17-18
4-5-6-7-8…18-19
5-6-7-8-9…19-20
Order Number: 320003-09
14-15-16-17-18-19-20-
15-16-17-18-19-20-21-
39). When a burst
7-8-9-10-11-12-13…
6-7-8-9-10-11-12-…
5-6-7-8-9-10-11…
4-5-6-7-8-9-10…
0-1-2-3-4-5-6-…
1-2-3-4-5-6-7-…
2-3-4-5-6-7-8-…
3-4-5-6-7-8-9-…
Figure 12,
…
…
P33-65nm
Mar 2010