DS21448 Maxim Integrated Products, DS21448 Datasheet - Page 44

• Manufacturer Part Number: DS21448
• Description: IC LIU QUAD E1/T1/J1 144-BGA
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS21448

• Number Of Drivers/receivers: 4/4
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 144-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Figure 8-2. TAP Controller State Diagram
Capture-DR. Data can be parallel-loaded into the test data registers selected by the current instruction. If the
instruction does not call for a parallel load or the selected register does not allow parallel loads, the test register
remains at its current value. On the rising edge of JTCLK, the controller goes to the shift-DR state if JTMS is LOW,
or it goes to the exit1-DR state if JTMS is HIGH.
Shift-DR. The test data register selected by the current instruction is connected between JTDI and JTDO, and
shifts data one stage toward its serial output on each rising edge of JTCLK. If a test register selected by the current
instruction is not placed in the serial path, it maintains its previous state.
Exit1-DR. While in this state, a rising edge on JTCLK puts the controller in the update-DR state, which terminates
the scanning process, if JTMS is HIGH. A rising edge on JTCLK with JTMS LOW puts the controller in the pause-
DR state.
Pause-DR. Shifting of the test registers is halted while in this state. All test registers selected by the current
instruction retain their previous state. The controller remains in this state while JTMS is LOW. A rising edge on
JTCLK with JTMS HIGH puts the controller in the exit2-DR state.
Exit2-DR. A rising edge on JTCLK with JTMS HIGH while in this state puts the controller in the update-DR state
and terminates the scanning process. A rising edge on JTCLK with JTMS LOW enters the shift-DR state.
Update-DR. A falling edge on JTCLK while in the update-DR state latches the data from the shift register path of
the test registers into the data output latches. This prevents changes at the parallel output due to changes in the
shift register.
1
0
Test Logic
Reset
Run Test/
Idle
0
1
0
1
Capture DR
Update DR
1
Pause DR
Select
DR-Scan
Exit2 DR
Shift DR
Exit DR
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0
1
0
0
1
0
1
1
0
0
1
0
1
Capture IR
Update IR
1
Pause IR
Select
IR-Scan
Shift IR
Exit2 IR
Exit IR
0
1
1
1
0
0
0
1
1
0
0