DS3150TN+ Maxim Integrated Products, DS3150TN+ Datasheet - Page 7

• Manufacturer Part Number: DS3150TN+
• Description: IC LIU T3/E3/STS-1 48-TQFP
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS3150TN+

• Number Of Drivers/receivers: 1/1
• Protocol: DS3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS3150
1.1 Receiver
Interfacing to the Line. The receiver can be transformer-coupled or capacitor-coupled to the line.
Typically, the receiver interfaces to the incoming coaxial cable (75W) through a 1:2 step-up transformer.
Figure 1-2
shows the arrangement of the transformer and other recommended interface components. The
device expects the incoming signal to be in B3ZS- or HDB3-coded AMI format.
Optional Preamp. The receiver can be used in monitoring applications, which typically have series
resistors that result in a resistive loss of approximately 20dB. When the RMON input pin is high, the
receiver compensates for this resistive loss by applying flat gain to the incoming signal before sending the
signal to the equalizer block.
Adaptive Equalizer. The adaptive equalizer applies both frequency-dependent gain and flat gain to
offset signal losses from the coaxial cable and provides a signal of nominal amplitude and pulse shape to
the clock and data recovery block. The equalizer circuitry automatically adapts to coaxial cable losses
from 0 to 15dB, which translates into 0 to 380 meters (DS3), 0 to 440 meters (E3), or 0 to 360 meters
(STS-1) of coaxial cable (AT&T 734A or equivalent). The equalizer can perform direct (0 meter)
monitoring of the transmitter output signal.
Clock and Data Recovery. The clock and data recovery (CDR) block takes the amplified, equalized
signal from the equalizer and produces separate clock, positive data and negative data signals. The CDR
requires a master clock (44.736MHz for DS3, 34.368MHz for E3, 51.840MHz for STS-1). If the signal
on MCLK is toggling, the device selects the MCLK signal as the master clock. If MCLK is wired high or
left floating, the device uses the signal on the TCLK pin as the master clock. If MCLK is wired low, the
device takes its master clock from an internal oscillator. The selected master clock is also used by the
jitter attenuator.
Loss-of-Signal Detector. The receiver contains both analog and digital LOS detectors. The analog
LOS detector resides in the equalizer block. If the incoming signal level is less than a signal level
approximately 24dB below nominal, analog loss-of-signal (ALOS) is declared. The ALOS signal cannot
be directly examined, but when ALOS occurs the equalizer squelches the recovered data, forcing all zeros
out of the clock and data recovery circuitry and subsequently causing digital loss-of-signal (DLOS),
which is indicated on the LOS pin. ALOS clears when the incoming signal level is greater than or equal
to a signal level approximately 18dB below nominal.
The digital loss-of-signal detector declares DLOS when it detects 175 ±75 consecutive zeros in the
recovered data stream. When DLOS occurs, the receiver asserts the LOS pin. DLOS is cleared when there
are no excessive zero occurrences over a span of 175 ±75 clock periods. An excessive zero occurrence is
defined as three or more consecutive zeros in the DS3 and STS-1 modes and four or more consecutive
zeros in the E3 mode. The LOS pin is deasserted when the DLOS condition is cleared.
The requirements of ANSI T1.231 and ITU-T G.775 for DS3 LOS defects are met by the DLOS detector,
which asserts LOS when it counts 175 ±75 consecutive zeros coming out of the clock and data recovery
block and clears LOS when it counts 175 ±75 consecutive pulse intervals without excessive zero
occurrences.
The requirements of ITU-T G.775 for E3 LOS defects are met by a combination of the ALOS detector
and the DLOS detector as follows:
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