CS5532-BS Cirrus Logic Inc, CS5532-BS Datasheet - Page 14

• Manufacturer Part Number: CS5532-BS
• Description: IC, ADC, 24BIT, 3.84KSPS, SSOP-20
• Manufacturer: Cirrus Logic Inc

Specifications of CS5532-BS

• Resolution (bits): 24bit
• Sampling Rate: 3.84kSPS
• Input Channel Type: Differential
• Data Interface: 3-Wire, Serial
• Supply Current: 13mA
• Digital Ic Case Style: SSOP
• No. Of Pins: 20
• Rohs Compliant: No

2. GENERAL DESCRIPTION
The CS5531/32/33/34 are highly integrated
alog-to-Digital Converters (ADCs) which use
charge-balance techniques to achieve 16-bit
(CS5531/33) and 24-bit (CS5532/34) performance.
The ADCs are optimized for measuring low-level
unipolar or bipolar signals in weigh scale, process
control, scientific, and medical applications.
To accommodate these applications, the ADCs
come as either two-channel (CS5531/32) or four-
channel (CS5533/34) devices and include a very
low noise chopper-stabilized programmable gain
instrumentation amplifier (PGIA, 6 nV/ Hz @ 0.1
Hz) with selectable gains of 1×, 2×, 4×, 8×, 16×,
32×, and 64×. These ADCs also include a fourth or-
der
provides twenty selectable output word rates of 6.25,
7.5, 12.5, 15, 25, 30, 50, 60, 100, 120, 200, 240, 400,
480, 800, 960, 1600, 1920, 3200, and 3840 Samples
per second (MCLK = 4.9152 MHz).
To ease communication between the ADCs and a
micro-controller, the converters include a simple
three-wire serial interface which is SPI and Mi-
14
AIN4+
AIN1+
AIN2+
AIN1+
AIN4-
AIN1-
AIN2-
AIN1-
modulator followed by a digital filter which
*
*
*
CS5531/32 IN+
CS5533/34
M
M
U
X
U
X
IN-
IN+
IN-
IN+
IN-
GAIN is the gain setting of the PGIA (i.e. 2, 4, 8, 16, 32, 64)
XGAIN
Figure 3. Multiplexer Configuration
X1
X1
1000
1000
22 nF
An-
C1 PIN
C2 PIN
crowire compatible with a Schmitt Trigger input on
the serial clock (SCLK).
2.1. Analog Input
Figure 3 illustrates a block diagram of the
CS5531/32/33/34. The front end consists of a multi-
plexer, a unity gain coarse/fine charge input buffer,
and a programmable gain chopper-stabilized instru-
mentation amplifier. The unity gain buffer is activat-
ed any time conversions are performed with a gain
of one and the instrumentation amplifier is activated
any time conversions are performed with gain set-
tings greater than one.
The unity gain buffer is designed to accommodate
rail to rail input signals. The common-mode plus
signal range for the unity gain buffer amplifier is
VA- to VA+. Typical CVF (sampling) current for
the unity gain buffer amplifier is about 500 nA
(MCLK = 4.9152 MHz, see Figure 4).
The instrumentation amplifier is chopper-stabi-
lized and operates with a chop clock frequency of
MCLK/128. The CVF (sampling) current into the
instrumentation amplifier is typically 500 pA over
VREF+
X1
Differential
Modulator
4 Order
th
VREF-
X1
Digital
Filter
Sinc
5
Programmable
Digital Filter
CS5531/32/33/34
Sinc
3
Serial
Port
DS289PP5