SC16C654BIEC NXP Semiconductors, SC16C654BIEC Datasheet - Page 10
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SC16C654BIEC
Manufacturer Part Number
SC16C654BIEC
Description
Manufacturer
NXP Semiconductors
Datasheet
1.SC16C654BIEC.pdf
(58 pages)
Specifications of SC16C654BIEC
Transmit Fifo
64Byte
Receive Fifo
64Byte
Transmitter And Receiver Fifo Counter
Yes
Data Rate
5Mbps
Operating Supply Voltage (max)
5.5V
Mounting
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SC16C654BIEC,528
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Company:
Part Number:
SC16C654BIEC,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Company:
Part Number:
SC16C654BIEC,557
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
Table 2:
9397 750 14965
Product data sheet
Symbol
16/68
A0
A1
A2
A3
A4
CDA
CDB
CDC
CDD
CLKSEL
CS
Pin
PLCC68 LQFP64 HVQFN48 LFBGA6
31
34
33
32
20
50
9
27
43
61
30
16
Pin description
5.2 Pin description
-
24
23
22
-
-
64
18
31
49
-
-
14
17
16
15
9
31
-
-
24
-
-
5
4
-
K5
J5
K4
-
-
A1
K2
J9
A10
-
-
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
Rev. 02 — 20 June 2005
Type Description
I
I
I
I
I
I
I
I
16/68 Interface type select (input with internal pull-up).
This input provides the 16 (Intel) or 68 (Motorola) bus
interface type select. The functions of IOR, IOW,
INTA to INTD, and CSA to CSD are re-assigned with the
logical state of this pin. When this pin is a logic 1, the
16 mode interface (16C654) is selected. When this pin is a
logic 0, the 68 mode interface (68C654) is selected. When
this pin is a logic 0, IOW is re-assigned to R/W, RESET is
re-assigned to RESET, IOR is not used, and INTA to INTD
are connected in a wire-OR configuration. The wire-OR
outputs are connected internally to the open-drain IRQ
signal output. This pin is not available on 64-pin packages
which operate in the 16 mode only.
Address 0 select bit. Internal registers address selection in
16 and 68 modes.
Address 1 select bit. Internal registers address selection in
16 and 68 modes.
Address 2 select bit. Internal registers address selection in
16 and 68 modes.
Address 3, Address 4 select bits. When the 68 mode is
selected, these pins are used to address or select individual
UARTs (providing CS is a logic 0). In the 16 mode, these
pins are re-assigned as chip selects, see CSB and CSC.
These pins are not available on 64-pin packages which
operate in the 16 mode only.
Carrier Detect (active LOW). These inputs are associated
with individual UART channels A through D. A logic 0 on this
pin indicates that a carrier has been detected by the modem
for that channel.
Clock Select. The 1 or 4 pre-scalable clock is selected by
this pin. The 1 clock is selected when CLKSEL is a logic 1
(connected to V
logic 0 (connected to GND). MCR[7] can override the state
of this pin following reset or initialization (see MCR[7]). This
pin is not available on 64-pin packages which provide
MCR[7] selection only.
Chip Select (active LOW). In the 68 mode, this pin
functions as a multiple channel chip enable. In this case, all
four UARTs (A to D) are enabled when the CS pin is a
logic 0. An individual UART channel is selected by the data
contents of address bits A[3:4]. when the 16 mode is
selected (68-pin devices), this pin functions as CSA (see
definition under CSA, CSB). This pin is not available on
64-pin packages which operate in the 16 mode only.
SC16C654B/654DB
CC
) or the 4 is selected when CLKSEL is a
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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