MT18HTF25672AZ-667H1 Micron Technology Inc, MT18HTF25672AZ-667H1 Datasheet - Page 15

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MT18HTF25672AZ-667H1

Manufacturer Part Number
MT18HTF25672AZ-667H1
Description
MODULE DDR2 SDRAM 2GB 240UDIMM
Manufacturer
Micron Technology Inc
Series
-r

Specifications of MT18HTF25672AZ-667H1

Main Category
DRAM Module
Sub-category
DDR2 SDRAM
Module Type
240UDIMM
Device Core Size
72b
Organization
256Mx72
Total Density
2GByte
Chip Density
1Gb
Access Time (max)
900ns
Maximum Clock Rate
667MHz
Operating Supply Voltage (typ)
1.8V
Operating Current
1.136A
Number Of Elements
18
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
240
Mounting
Socket
Memory Type
DDR2 SDRAM
Memory Size
2GB
Speed
667MT/s
Features
-
Package / Case
240-UDIMM
Lead Free Status / Rohs Status
Compliant
Table 12: DDR2 I
Values shown for MT47H256M8 DDR2 SDRAM only and are computed from values specified in the 2Gb (256 Meg x 8) com-
ponent data sheet
PDF: 09005aef83c6d17f
htf18c256_512x72az.fm - Rev. B 2/10 EN
Parameter
Operating one bank active-precharge current:
t
inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
(I
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching;
Data pattern is same as I
Precharge power-down current: All device banks idle;
Other control and address bus inputs are stable; Data bus inputs are floating
Precharge quiet standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs
are floating
Precharge standby current: All device banks idle;
HIGH; Other control and address bus inputs are switching; Data bus inputs are switch-
ing
Active power-down current: All device banks open;
(I
Data bus inputs are floating
Active standby current: All device banks open;
(I
and address bus inputs are switching; Data bus inputs are switching
Operating burst write current: All device banks open; Continuous burst writes; BL
= 4, CL = CL (I
HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data
bus inputs are switching
Operating burst read current: All device banks open; Continuous burst read, I
= 0mA; BL = 4, CL = CL (I
(I
ing; Data bus inputs are switching
Burst refresh current:
val; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus
inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus
inputs are floating; Data bus inputs are floating
RAS =
DD
DD
DD
DD
), AL = 0;
); CKE is LOW; Other control and address bus inputs are stable;
),
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switch-
t
RP =
t
RAS MIN (I
t
RP (I
t
DD
CK =
), AL = 0;
DD
DD
); CKE is HIGH, S# is HIGH between valid commands; Other control
t
DD
CK (I
); CKE is HIGH, S# is HIGH between valid commands; Address bus
Specifications and Conditions – 4GB
t
DD
DD
DD4W
CK =
t
CK =
),
), AL = 0;
t
RC =
t
CK (I
t
CK (I
t
RC (I
DD
t
DD
CK =
); REFRESH command at every
),
DD
t
RAS =
),
t
CK (I
2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM UDIMM
t
RAS =
DD
t
RAS MAX (I
),
t
CK =
t
t
RAS MIN (I
t
CK =
RAS =
t
CK =
t
CK =
t
CK (I
t
CK (I
t
OUT
CK =
t
t
t
CK (I
RAS MAX (I
CK =
DD
15
t
DD
CK
= 0mA; BL = 4, CL = CL
DD
),
DD
),
t
DD
t
),
CK (I
),
RP =
t
t
CK (I
); CKE is HIGH, S# is
RAS =
t
t
RCD =
RC =
t
RFC (I
DD
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
t
DD
Micron Technology, Inc. reserves the right to change products or specifications without notice.
RP (I
DD
); CKE is LOW;
t
t
); CKE is
RC (I
RAS MAX
),
t
RCD (I
DD
DD
t
RP =
) inter-
); CKE is
DD
),
DD
t
OUT
RP
);
Symbol
I
I
I
I
I
I
I
DD4W
DD2Q
I
I
DD2N
DD3N
DD4R
I
I
DD2P
DD3P
DD0
DD1
DD5
DD6
1
1
2
2
2
2
1
2
2
2
1
© 2009 Micron Technology, Inc. All rights reserved.
I
DD
-80E/
-800
1000
1400
1040
1120
1040
1520
1600
4800
160
720
224
160
Specifications
1240
1280
1440
4480
-667
880
160
880
960
640
224
880
160
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA

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