PIC32MX795F512HT-80V/MR Microchip Technology, PIC32MX795F512HT-80V/MR Datasheet - Page 54
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PIC32MX795F512HT-80V/MR
Manufacturer Part Number
PIC32MX795F512HT-80V/MR
Description
512 KB Flash, 128 KB RAM, USB-OTG, Dual CAN, Ethernet, 80 MHz, 10-Bit ADC, DMA 6
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheet
1.PIC32MX575F256H-80VPT.pdf
(256 pages)
Specifications of PIC32MX795F512HT-80V/MR
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, Ethernet, I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
64-VFQFN Exposed Pad
Core
MIPS
Processor Series
PIC32MX7xx
Data Bus Width
32 bit
Maximum Clock Frequency
80 MHz
Data Ram Size
64 KB
Number Of Programmable I/os
5
Number Of Timers
5
Operating Supply Voltage
2.3 V to 3.6 V
Operating Temperature Range
- 40 C to + 85 C
Mounting Style
SMD/SMT
Interface Type
USB, I2C, UART, RS-232, RS-485, SPI
Maximum Operating Temperature
+ 85 C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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supports slowing or Halting the clocks, which reduces
PIC32MX5XX/6XX/7XX
3.3
The MIPS M4K Processor core offers a number of
power management features, including low-power
design, active power management and power-down
modes of operation. The core is a static design that
system power consumption during Idle periods.
3.3.1
The mechanism for invoking Power-Down mode is
through execution of the WAIT instruction. For more
information on power management, see
“Power-Saving
3.3.2
The majority of the power consumed by the
PIC32MX5XX/6XX/7XX family core is in the clock tree
and clocking registers. The PIC32 family uses exten-
sive use of local gated clocks to reduce this dynamic
power consumption.
DS61156G-page 54
Power Management
INSTRUCTION-CONTROLLED
POWER MANAGEMENT
LOCAL CLOCK GATING
Features”.
Section 27.0
3.4
The MIPS M4K Processor core provides for an
Enhanced JTAG (EJTAG) interface for use in the soft-
ware debug of application and kernel code. In addition
to standard User mode and Kernel modes of operation,
the MIPS M4K core provides a Debug mode that is
entered after a debug exception (derived from a hard-
ware breakpoint, single-step exception, etc.) is taken
and continues until a Debug Exception Return (DERET)
instruction is executed. During this time, the processor
executes the debug exception handler routine.
The EJTAG interface operates through the Test Access
Port (TAP), a serial communication port used for trans-
ferring test data in and out of the MIPS M4K processor
core. In addition to the standard JTAG instructions,
special instructions defined in the EJTAG specification
define which registers are selected and how they are
used.
EJTAG Debug Support
© 2009-2011 Microchip Technology Inc.
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