PIC32MX795F512HT-80V/MR Microchip Technology, PIC32MX795F512HT-80V/MR Datasheet - Page 52
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PIC32MX795F512HT-80V/MR
Manufacturer Part Number
PIC32MX795F512HT-80V/MR
Description
512 KB Flash, 128 KB RAM, USB-OTG, Dual CAN, Ethernet, 80 MHz, 10-Bit ADC, DMA 6
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheet
1.PIC32MX575F256H-80VPT.pdf
(256 pages)
Specifications of PIC32MX795F512HT-80V/MR
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, Ethernet, I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
64-VFQFN Exposed Pad
Core
MIPS
Processor Series
PIC32MX7xx
Data Bus Width
32 bit
Maximum Clock Frequency
80 MHz
Data Ram Size
64 KB
Number Of Programmable I/os
5
Number Of Timers
5
Operating Supply Voltage
2.3 V to 3.6 V
Operating Temperature Range
- 40 C to + 85 C
Mounting Style
SMD/SMT
Interface Type
USB, I2C, UART, RS-232, RS-485, SPI
Maximum Operating Temperature
+ 85 C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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PIC32MX5XX/6XX/7XX
TABLE 3-2:
DS61156G-page 52
Note 1:
Register
Number
17-22
25-29
0-6
10
11
12
12
12
12
13
14
15
15
16
16
16
16
23
24
30
31
7
8
9
2:
Registers used in exception processing.
Registers used during debug.
Reserved
HWREna
BadVAddr
Count
Reserved
Compare
Status
IntCtl
SRSCtl
SRSMap
Cause
EPC
PRId
EBASE
Config
Config1
Config2
Config3
Reserved
Debug
DEPC
Reserved
ErrorEPC
DESAVE
(1)
(1)
Register
(1)
COPROCESSOR 0 REGISTERS
(1)
(2)
(1)
(2)
Name
(1)
(1)
(2)
(1)
(1)
(1)
Reserved.
Enables access via the RDHWR instruction to selected hardware registers.
Reports the address for the most recent address-related exception.
Processor cycle count.
Reserved.
Timer interrupt control.
Processor status and control.
Interrupt system status and control.
Shadow register set status and control.
Provides mapping from vectored interrupt to a shadow set.
Cause of last general exception.
Program counter at last exception.
Processor identification and revision.
Exception vector base register.
Configuration register.
Configuration Register 1.
Configuration Register 2.
Configuration Register 3.
Reserved.
Debug control and exception status.
Program counter at last debug exception.
Reserved.
Program counter at last error.
Debug handler scratchpad register.
Function
© 2009-2011 Microchip Technology Inc.
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